2020-02-20 22:03:34 +01:00
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// Copyright 2019 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package cpu
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import "runtime"
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const cacheLineSize = 64
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2020-09-22 19:02:16 +02:00
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func initOptions() {
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options = []option{
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{Name: "fp", Feature: &ARM64.HasFP},
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{Name: "asimd", Feature: &ARM64.HasASIMD},
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{Name: "evstrm", Feature: &ARM64.HasEVTSTRM},
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{Name: "aes", Feature: &ARM64.HasAES},
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{Name: "fphp", Feature: &ARM64.HasFPHP},
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{Name: "jscvt", Feature: &ARM64.HasJSCVT},
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{Name: "lrcpc", Feature: &ARM64.HasLRCPC},
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{Name: "pmull", Feature: &ARM64.HasPMULL},
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{Name: "sha1", Feature: &ARM64.HasSHA1},
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{Name: "sha2", Feature: &ARM64.HasSHA2},
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{Name: "sha3", Feature: &ARM64.HasSHA3},
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{Name: "sha512", Feature: &ARM64.HasSHA512},
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{Name: "sm3", Feature: &ARM64.HasSM3},
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{Name: "sm4", Feature: &ARM64.HasSM4},
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{Name: "sve", Feature: &ARM64.HasSVE},
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{Name: "crc32", Feature: &ARM64.HasCRC32},
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{Name: "atomics", Feature: &ARM64.HasATOMICS},
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{Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
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{Name: "cpuid", Feature: &ARM64.HasCPUID},
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{Name: "asimrdm", Feature: &ARM64.HasASIMDRDM},
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{Name: "fcma", Feature: &ARM64.HasFCMA},
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{Name: "dcpop", Feature: &ARM64.HasDCPOP},
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{Name: "asimddp", Feature: &ARM64.HasASIMDDP},
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{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
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}
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}
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func archInit() {
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2020-02-20 22:03:34 +01:00
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switch runtime.GOOS {
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2020-10-16 07:06:27 +02:00
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case "android", "darwin", "ios", "netbsd":
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2020-02-20 22:03:34 +01:00
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// Android and iOS don't seem to allow reading these registers.
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2020-06-18 01:29:38 +02:00
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//
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// NetBSD:
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// ID_AA64ISAR0_EL1 is a privileged register and cannot be read from EL0.
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// It can be read via sysctl(3). Example for future implementers:
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// https://nxr.netbsd.org/xref/src/usr.sbin/cpuctl/arch/aarch64.c
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//
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2020-02-20 22:03:34 +01:00
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// Fake the minimal features expected by
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// TestARM64minimalFeatures.
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ARM64.HasASIMD = true
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ARM64.HasFP = true
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case "linux":
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doinit()
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default:
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readARM64Registers()
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}
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}
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func readARM64Registers() {
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Initialized = true
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// ID_AA64ISAR0_EL1
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isar0 := getisar0()
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switch extractBits(isar0, 4, 7) {
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case 1:
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ARM64.HasAES = true
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case 2:
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ARM64.HasAES = true
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ARM64.HasPMULL = true
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}
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switch extractBits(isar0, 8, 11) {
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case 1:
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ARM64.HasSHA1 = true
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}
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switch extractBits(isar0, 12, 15) {
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case 1:
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ARM64.HasSHA2 = true
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case 2:
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ARM64.HasSHA2 = true
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ARM64.HasSHA512 = true
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}
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switch extractBits(isar0, 16, 19) {
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case 1:
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ARM64.HasCRC32 = true
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}
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switch extractBits(isar0, 20, 23) {
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case 2:
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ARM64.HasATOMICS = true
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}
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switch extractBits(isar0, 28, 31) {
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case 1:
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ARM64.HasASIMDRDM = true
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}
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switch extractBits(isar0, 32, 35) {
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case 1:
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ARM64.HasSHA3 = true
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}
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switch extractBits(isar0, 36, 39) {
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case 1:
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ARM64.HasSM3 = true
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}
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switch extractBits(isar0, 40, 43) {
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case 1:
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ARM64.HasSM4 = true
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}
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switch extractBits(isar0, 44, 47) {
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case 1:
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ARM64.HasASIMDDP = true
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}
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// ID_AA64ISAR1_EL1
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isar1 := getisar1()
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switch extractBits(isar1, 0, 3) {
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case 1:
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ARM64.HasDCPOP = true
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}
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switch extractBits(isar1, 12, 15) {
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case 1:
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ARM64.HasJSCVT = true
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}
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switch extractBits(isar1, 16, 19) {
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case 1:
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ARM64.HasFCMA = true
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}
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switch extractBits(isar1, 20, 23) {
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case 1:
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ARM64.HasLRCPC = true
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}
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// ID_AA64PFR0_EL1
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pfr0 := getpfr0()
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switch extractBits(pfr0, 16, 19) {
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case 0:
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ARM64.HasFP = true
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case 1:
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ARM64.HasFP = true
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ARM64.HasFPHP = true
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}
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switch extractBits(pfr0, 20, 23) {
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case 0:
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ARM64.HasASIMD = true
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case 1:
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ARM64.HasASIMD = true
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ARM64.HasASIMDHP = true
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}
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switch extractBits(pfr0, 32, 35) {
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case 1:
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ARM64.HasSVE = true
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}
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}
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func extractBits(data uint64, start, end uint) uint {
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return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
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}
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