187 lines
3.7 KiB
ArmAsm
187 lines
3.7 KiB
ArmAsm
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// TITLE("Miscellaneous Kernel Functions")
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//++
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//
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// Copyright (c) 1991 Microsoft Corporation
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//
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// Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// pxflshbf.s
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//
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// Abstract:
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//
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// This module implements the system dependent kernel function to flush
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// the write buffer or otherwise synchronize writes on a Power PC
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// system.
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//
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//
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//
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// Author:
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//
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// David N. Cutler (davec) 24-Apr-1991
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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//
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// Jim Wooldridge (jimw@austin.vnet.ibm.com) Initial PowerPC port
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//
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// Used PowerPC eieio instruction to flush writes
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//
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//--
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#include "kxppc.h"
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.extern HalpIoControlBase
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.set ISA, r.7
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// SBTTL("Flush Write Buffer")
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//
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//++
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//
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// NTSTATUS
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// KeFlushWriteBuffer (
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// VOID
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// )
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//
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// Routine Description:
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//
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// This function flushes the write buffer on the current processor.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(KeFlushWriteBuffer)
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//
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// It is required that the results of all stores to memory and I/O registers,
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// performed in "critical sections" just prior to calling KeFlushWriteBuffer,
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// be seen by other processors and mechanisms before returning from this
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// routine (KeFlushWriteBuffer). All write-posting queues, both processor and
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// external hardware, must be flushed so that their data are seen by other
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// processors and controllers on both the PCI and ISA busses.
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//
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//
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// The Eagle will initiate flushing it's write posting queue on either
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// an EIEIO or a SYNC. However, an EIEIO is a NOP on a 603, so we use
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// a LOAD from ISA I/O space to get the same effect.
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//
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eieio //
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lwz r.4,[toc]HalpIoControlBase(r.toc)
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lwz r.4,0(r.4)
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lbz r.4, 0x21(r.4)
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//
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// Lastly, theFlush write buffers on the processor! To do this, we must use the
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// "sync" instruction. The EIEIO instruction does NOT provide the required
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// synchronization with external hardware and controllers.
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//
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sync
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LEAF_EXIT(KeFlushWriteBuffer)
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LEAF_ENTRY(HalpPatch_KeFlushWriteBuffer)
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mflr r.8 // Save LR
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bl Here
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Here: mflr r.9
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mtlr r.8 // Restore LR
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addi r.3, r.9, ..HalpFlushWriteBuffer603-Here
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addi r.4, r.9, ..HalpFlushWriteBuffer604-Here
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mfpvr r.0 // Distinguish 603/603e from 604/604e
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andis. r.0, r.0, 0x0002
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beq PatchTOC
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mr r.4, r.3
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PatchTOC:
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lwz r.7, [toc]KeFlushWriteBuffer(r.toc)
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stw r.4, 0(r.7)
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dcbf r.0, r.7 // Flush it from the L1 cache
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LEAF_EXIT(HalpPatch_KeFlushWriteBuffer)
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LEAF_ENTRY(HalpFlushWriteBuffer603)
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lwz r.4,[toc]HalpIoControlBase(r.toc)
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lwz r.4,0(r.4)
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lbz r.4, 0x21(r.4)
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sync
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LEAF_EXIT(HalpFlushWriteBuffer603)
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LEAF_ENTRY(HalpFlushWriteBuffer604)
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eieio // Initiate flushing the Eagle write-post buffers
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sync // Wait for the flushing to complete
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LEAF_EXIT(HalpFlushWriteBuffer604)
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//
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//++
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//
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// NTSTATUS
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// HalpSynchronizeExecution()
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// VOID
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// )
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//
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// Routine Description:
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//
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// This function flushes the write buffer on the current processor.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSynchronizeExecution)
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sync // synchronize
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LEAF_EXIT(HalpSynchronizeExecution)
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//
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//++
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//
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// VOID
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// HalpSetSDR1(
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// ULONG HashedPageTableBase,
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// ULONG HashedPageTableSize
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// )
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//
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// HashedPageTableSize is unused because we ASSUME that the HPT is 64K
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//
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LEAF_ENTRY(HalpSetSDR1)
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mtsdr1 r.3
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LEAF_EXIT(HalpSetSDR1)
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