520 lines
18 KiB
C
520 lines
18 KiB
C
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/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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sable.h
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Abstract:
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This file defines the structures and definitions common to all
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sable-based platforms.
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Author:
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Joe Notarangelo 26-Oct-1993
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Steve Jenness 26-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef _SABLEH_
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#define _SABLEH_
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#include "sableref.h" // Sable reference I/O structure
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#include "lynxref.h" // Lynx interrupt structure
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#include "xioref.h" // XIO interrupt structure
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#if !defined(_LANGUAGE_ASSEMBLY)
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#include "errframe.h"
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#endif
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//
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// Constants used by dense space I/O routines
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//
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#define SABLE_PCI0_DENSE_BASE_PHYSICAL_SUPERPAGE 0xfffffc03c0000000
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#define SABLE_PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE 0xfffffc0180000000
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#define PCI_DENSE_BASE_PHYSICAL_SUPERPAGE \
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(SABLE_PCI0_DENSE_BASE_PHYSICAL_SUPERPAGE - SABLE_PCI0_DENSE_MEMORY_QVA)
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#define PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE \
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(SABLE_PCI1_DENSE_BASE_PHYSICAL_SUPERPAGE - SABLE_PCI1_DENSE_MEMORY_QVA)
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#if !defined(_LANGUAGE_ASSEMBLY)
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#include "t2.h" // T2 chipset definitions
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#include "icic.h" // ICIC definitions
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//
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// QVA
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// HAL_MAKE_QVA(
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// ULONGLONG PhysicalAddress
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// )
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//
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// Routine Description:
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//
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// This macro returns the Qva for a physical address in system space.
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//
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// Arguments:
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//
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// PhysicalAddress - Supplies a 64-bit physical address.
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//
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// Return Value:
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//
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// The Qva associated with the physical address.
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//
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#define HAL_MAKE_QVA(PA) \
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( (PVOID)( QVA_ENABLE | (ULONG)(PA >> IO_BIT_SHIFT) ) )
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//
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// Define physical address spaces for SABLE.
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//
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// PCI0 - 32bit PCI bus
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// PCI1 - 64bit PCI bus
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//
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#define SABLE_PCI1_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x180000000)
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#define SABLE_PCI1_SPARSE_IO_PHYSICAL ((ULONGLONG)0x1C0000000)
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#define SABLE_PCI0_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x200000000)
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#define SABLE_PCI1_SPARSE_MEMORY_PHYSICAL ((ULONGLONG)0x300000000)
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#define SABLE_CBUS_CSRS_PHYSICAL ((ULONGLONG)0x380000000)
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#define SABLE_CPU0_CSRS_PHYSICAL ((ULONGLONG)0x380000000)
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#define SABLE_CPU1_CSRS_PHYSICAL ((ULONGLONG)0x381000000)
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#define SABLE_CPU2_CSRS_PHYSICAL ((ULONGLONG)0x382000000)
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#define SABLE_CPU3_CSRS_PHYSICAL ((ULONGLONG)0x383000000)
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#define SABLE_CPU0_IPIR_PHYSICAL ((ULONGLONG)0x380000160)
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#define SABLE_CPU1_IPIR_PHYSICAL ((ULONGLONG)0x381000160)
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#define SABLE_CPU2_IPIR_PHYSICAL ((ULONGLONG)0x382000160)
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#define SABLE_CPU3_IPIR_PHYSICAL ((ULONGLONG)0x383000160)
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#define SABLE_MEM0_CSRS_PHYSICAL ((ULONGLONG)0x388000000)
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#define SABLE_MEM1_CSRS_PHYSICAL ((ULONGLONG)0x389000000)
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#define SABLE_MEM2_CSRS_PHYSICAL ((ULONGLONG)0x38A000000)
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#define SABLE_MEM3_CSRS_PHYSICAL ((ULONGLONG)0x38B000000)
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#define SABLE_T2_CSRS_PHYSICAL ((ULONGLONG)0x38E000000)
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#define SABLE_T4_CSRS_PHYSICAL ((ULONGLONG)0x38F000000)
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#define T2_CSRS_QVA (HAL_MAKE_QVA(SABLE_T2_CSRS_PHYSICAL))
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#define T4_CSRS_QVA (HAL_MAKE_QVA(SABLE_T4_CSRS_PHYSICAL))
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#define SABLE_PCI0_CONFIGURATION_PHYSICAL ((ULONGLONG)0x390000000)
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#define SABLE_PCI1_CONFIGURATION_PHYSICAL ((ULONGLONG)0x398000000)
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#define SABLE_PCI0_SPARSE_IO_PHYSICAL ((ULONGLONG)0x3A0000000)
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#define SABLE_PCI0_DENSE_MEMORY_PHYSICAL ((ULONGLONG)0x3C0000000)
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//
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// Define the limits of User mode Sparse and Dense space:
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//
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#define SABLE_USER_PCI1_DENSE_MEMORY_PHYSICAL (ULONGLONG)0x180000000
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#define SABLE_USER_PCI1_SPARSE_IO_PHYSICAL (ULONGLONG)0x1C0000000
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#define SABLE_USER_PCI1_SPARSE_IO_END_PHYSICAL (ULONGLONG)0x1E0000000
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#define SABLE_USER_PCI0_SPARSE_MEMORY_PHYSICAL (ULONGLONG)0x200000000
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#define SABLE_USER_PCI0_SPARSE_MEMORY_END_PHYSICAL (ULONGLONG)0x300000000
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#define SABLE_USER_PCI1_SPARSE_MEMORY_PHYSICAL (ULONGLONG)0x300000000
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#define SABLE_USER_PCI1_SPARSE_MEMORY_END_PHYSICAL (ULONGLONG)0x380000000
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#define SABLE_USER_PCI0_SPARSE_IO_PHYSICAL (ULONGLONG)0x3A0000000
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#define SABLE_USER_PCI0_SPARSE_IO_END_PHYSICAL (ULONGLONG)0x3C0000000
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#define SABLE_USER_PCI0_DENSE_MEMORY_PHYSICAL (ULONGLONG)0x3C0000000
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#define SABLE_EDGE_LEVEL_CSRS_PHYSICAL ((ULONGLONG)0x3A00004C0)
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#define SABLE_INTERRUPT_CSRS_PHYSICAL ((ULONGLONG)0x3A000A640)
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#define XIO_INTERRUPT_CSRS_PHYSICAL ((ULONGLONG)0x1C0000530)
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#define XIO_INTERRUPT_CSRS_QVA (HAL_MAKE_QVA(XIO_INTERRUPT_CSRS_PHYSICAL))
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//
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// Define Interrupt Controller CSRs.
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//
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#define SABLE_EDGE_LEVEL_CSRS_QVA (HAL_MAKE_QVA(SABLE_EDGE_LEVEL_CSRS_PHYSICAL))
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#define SABLE_INTERRUPT_CSRS_QVA (HAL_MAKE_QVA(SABLE_INTERRUPT_CSRS_PHYSICAL))
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//
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// Define the XIO_VECTOR <CIRQL1>
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//
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#define XIO_VECTOR UNUSED_VECTOR
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//
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// Define CPU CSRs and masks.
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//
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#define SABLE_CPU0_CSRS_QVA (HAL_MAKE_QVA(SABLE_CPU0_CSRS_PHYSICAL))
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#define SABLE_CPU1_CSRS_QVA (HAL_MAKE_QVA(SABLE_CPU1_CSRS_PHYSICAL))
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#define SABLE_CPU2_CSRS_QVA (HAL_MAKE_QVA(SABLE_CPU2_CSRS_PHYSICAL))
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#define SABLE_CPU3_CSRS_QVA (HAL_MAKE_QVA(SABLE_CPU3_CSRS_PHYSICAL))
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#define SABLE_MEM0_CSRS_QVA (HAL_MAKE_QVA(SABLE_MEM0_CSRS_PHYSICAL))
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#define SABLE_MEM1_CSRS_QVA (HAL_MAKE_QVA(SABLE_MEM1_CSRS_PHYSICAL))
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#define SABLE_MEM2_CSRS_QVA (HAL_MAKE_QVA(SABLE_MEM2_CSRS_PHYSICAL))
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#define SABLE_MEM3_CSRS_QVA (HAL_MAKE_QVA(SABLE_MEM3_CSRS_PHYSICAL))
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#define SABLE_PRIMARY_PROCESSOR ((ULONG)0x0)
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#define SABLE_SECONDARY_PROCESSOR ((ULONG)0x1)
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#define SABLE_MAXIMUM_PROCESSOR ((ULONG)0x3)
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#define HAL_PRIMARY_PROCESSOR (SABLE_PRIMARY_PROCESSOR)
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#define HAL_MAXIMUM_PROCESSOR (SABLE_MAXIMUM_PROCESSOR)
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//
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// Define the default processor frequency to be used before the actual
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// frequency can be determined.
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//
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#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (275)
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enum {
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NoError,
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UncorrectableError,
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CorrectableError
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} ErrorType;
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//
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// Define the list of CSR's...
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//
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typedef struct _SABLE_CPU_CSRS {
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UCHAR Bcc; // B-Cache Control Register
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UCHAR Bcce; // B-Cache Correctable Error Register
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UCHAR Bccea; // B-Cache Correctable Error Address Register
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UCHAR Bcue; // B-Cache Uncorrectable Error Register
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UCHAR Bcuea; // B-Cache Uncorrectable Error Address Register
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UCHAR Dter; // Duplicate Tag Error Register
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UCHAR Cbctl; // System Bus Control Register
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UCHAR Cb2; // System Bus Error Register
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UCHAR Cbeal; // System Bus Error Address Low Register
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UCHAR Cbeah; // System Bus Error Address High Register
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UCHAR Pmbx; // Processor Mailbox Register
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UCHAR Ipir; // Inter-Processor Interrupt Request Register
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UCHAR Sic; // System Interrupt Clear Register
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UCHAR Adlk; // Address Lock Register
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UCHAR Madrl; // Miss Address Register
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UCHAR Crrevs; // C4 Revision Register
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} SABLE_CPU_CSRS, *PSABLE_CPU_CSRS;
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//
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// Define the System Bus Control Register
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//
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typedef struct _SABLE_CBCTL_CSR{
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ULONG DataWrongParity: 1; // 0
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ULONG CaWrongParity: 2; // 1
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ULONG EnableParityCheck: 1; // 3
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ULONG ForceShared: 1; // 4
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ULONG CommaderId: 3; // 5
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ULONG Reserved0: 3; // 8
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ULONG EnableCbusErrorInterrupt: 1; // 11
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ULONG Reserved1: 1; // 12
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ULONG SecondQuadwordSelect: 1; // 13
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ULONG SelectDrack: 1; // 14
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ULONG Reserved2: 17; // 15
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ULONG DataWrongParityHigh: 1; // 32
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ULONG CaWrongParityHigh: 2; // 33
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ULONG EnableParityCheckHigh: 1; // 35
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ULONG ForceSharedHigh: 1; // 36
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ULONG CommanderIdHigh: 3; // 37
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ULONG Reserved3: 3; // 40
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ULONG EnableCbusErrorInterruptHigh: 1; // 43
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ULONG DisableBackToBackArbitration: 1; // 44
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ULONG SecondQuadwordSelectHigh: 1; // 45
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ULONG SelectDrackHigh: 1; // 46
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ULONG Reserved4: 17; // 47
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} SABLE_CBCTL_CSR, *PSABLE_CBCTL_CSR;
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//
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// Define all the System Bus (CobraBus or CBus) Control and Error Registers
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// listed above: Bcc, Bcce, Bccea, Bcue, Bcuea
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//
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typedef struct _SABLE_BCACHE_BCC_CSR0 {
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union {
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ULONG EnableAllocateL: 1; // 0
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ULONG ForceFillSharedL: 1; // 1
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ULONG EnbTagParCheckL: 1; // 2
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ULONG FillWrongTagParL: 1; // 3
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ULONG FillWrongContolParL: 1; // 4
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ULONG FillWrongDupTagStoreParL: 1; // 5
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ULONG EnableCorrectableErrorInterruptL: 1; // 6
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ULONG EnableEDCCorrectionL: 1; // 7
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ULONG EnableEDCCheckL: 1; // 8
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ULONG EnableBCacheConditionIOUpdatesL: 1; // 9
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ULONG DisableBlockWriteAroundL: 1; // 10
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ULONG EnableBCacheInitL: 1; // 11
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ULONG ForceEDCControlL: 1; // 12
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ULONG SharedDirtyValidL: 3; // 13-15
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ULONG EDCL: 14; // 16-29
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ULONG Reserved1: 1; // 30
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ULONG CacheSizeL: 1; // 31
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ULONG EnableAllocateH: 1; // 32
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ULONG ForceFillSharedH: 1; // 33
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ULONG EnbTagParCheckH: 1; // 34
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ULONG FillWronTagParH: 1; // 35
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ULONG FillWrongContolParH: 1; // 36
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ULONG FillWrongDupTagStoreParH: 1; // 37
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ULONG EnableCorrectableErrorInterruptH: 1; // 38
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ULONG EnableEDCCorrectionH: 1; // 39
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ULONG EnableEDCCheckH: 1; // 40
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ULONG EnableBCacheConditionIOUpdatesH: 1; // 41
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ULONG DisableBlockWriteAroundH: 1; // 42
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ULONG EnableBCacheInitH: 1; // 43
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ULONG ForceEDCControlH: 1; // 44
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ULONG SharedDirtyValidH: 3; // 45-47
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ULONG EDCH: 14; // 48-61
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ULONG Reserved2: 1; // 62
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ULONG CacheSizeH: 1; // 63
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};
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ULONGLONG all;
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} SABLE_BCACHE_BCC_CSR0, *PSABLE_BCACHE_BCC_CSR0;
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//
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// Define the Backup Cache correctable error register
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//
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typedef struct _SABLE_BCACHE_BCCE_CSR1 {
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union {
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ULONG Reserved1: 2; // 0-1
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ULONG MissedCorrectableError: 1; // 2
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ULONG CorrectableError: 1; // 3
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ULONG Reserved2: 4; // 4-7
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ULONG ControlBitParity: 1; // 8
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ULONG Shared: 1; // 9
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ULONG Dirty: 1; // 10
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ULONG Valid: 1; // 11
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ULONG Reserved3: 5; // 12-16
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ULONG EDCError1: 1; // 17
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ULONG EDCSyndrome0: 7; // 18-24
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ULONG EDCSyndrome2: 7; // 25-31
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ULONG Reserved4: 2; // 32-33
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ULONG MissedCorrectableErrorH: 1; // 34
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ULONG CorrectableErrorH: 1; // 35
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ULONG Undefined: 13; // 36-48
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ULONG EDCError2: 1; // 49
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ULONG EDCSyndrome1: 7; // 50-56
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ULONG EDCSyndrome3: 7; // 57-63
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};
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ULONGLONG all;
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} SABLE_BCACHE_BCCE_CSR1, *PSABLE_BCACHE_BCCE_CSR1;
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//
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// Define the Backup Cache correctable error address register
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//
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typedef struct _SABLE_BCACHE_BCCEA_CSR2 {
|
|||
|
|
union {
|
|||
|
|
ULONG BcacheMapOffsetL: 17; // 0-16
|
|||
|
|
ULONG Reserved1: 1; // 17
|
|||
|
|
ULONG TagParityL: 1; // 18
|
|||
|
|
ULONG TagValueL: 12; // 19-30
|
|||
|
|
ULONG Reserved2: 1; // 31
|
|||
|
|
ULONG BcacheMapOffsetH: 17; // 32-48
|
|||
|
|
ULONG Reserved3: 1; // 49
|
|||
|
|
ULONG TagParityH: 1; // 50
|
|||
|
|
ULONG TagValueH: 12; // 51-62
|
|||
|
|
ULONG Reserved4: 1; // 63
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
|
|||
|
|
} SABLE_BCACHE_BCCEA_CSR2, *PSABLE_BCACHE_BCCEA_CSR2;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the Backup Cache uncorrectable error register
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef struct _SABLE_BCACHE_BCUE_CSR3 {
|
|||
|
|
union {
|
|||
|
|
ULONG MissedParErrorL: 1; // 0
|
|||
|
|
ULONG ParityErrorL: 1; // 1
|
|||
|
|
ULONG MissedUncorrectableErrorL: 1; // 2
|
|||
|
|
ULONG UncorrectableErrorL: 1; // 3
|
|||
|
|
ULONG Reserved1: 4; // 4-7
|
|||
|
|
ULONG ControlBitParityL: 1; // 8
|
|||
|
|
ULONG Shared: 1; // 9
|
|||
|
|
ULONG Dirty: 1; // 10
|
|||
|
|
ULONG Valid: 1; // 11
|
|||
|
|
ULONG Resrved2: 5; // 12-16
|
|||
|
|
ULONG BCacheEDCError1: 1; // 17
|
|||
|
|
ULONG EDCSyndrome0: 7; // 18-24
|
|||
|
|
ULONG EDCSyndrome2: 7; // 25-31
|
|||
|
|
ULONG MissedParErrorH: 1; // 32
|
|||
|
|
ULONG ParityErrorH: 1; // 33
|
|||
|
|
ULONG MissedUncorrectableErrorH: 1; // 34
|
|||
|
|
ULONG UncorrectableErrorH: 1; // 35
|
|||
|
|
ULONG Resreved3: 13; // 36-48
|
|||
|
|
ULONG BCacheEDCError2: 1; // 49
|
|||
|
|
ULONG EDCSyndrome1: 7; // 50-56
|
|||
|
|
ULONG EDCSyndrome3: 7; // 57-63
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
|
|||
|
|
} SABLE_BCACHE_BCUE_CSR3, *PSABLE_BCACHE_BCUE_CSR3;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the Backup Cache uncorrectable error address register
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef struct _SABLE_BCACHE_BCUEA_CSR4 {
|
|||
|
|
union {
|
|||
|
|
ULONG BCacheMapOffsetL: 17; // 0-16
|
|||
|
|
ULONG PredictedTagParL: 1; // 17
|
|||
|
|
ULONG TagParityL: 1; // 18
|
|||
|
|
ULONG TagValueL: 12; // 19-30
|
|||
|
|
ULONG Reserved1: 1; // 31
|
|||
|
|
ULONG BCacheMapOffsetH: 17; // 32-48
|
|||
|
|
ULONG PredictedTagParH: 1; // 49
|
|||
|
|
ULONG TagParityJ: 1; // 50
|
|||
|
|
ULONG TagValueH: 12; // 51-62
|
|||
|
|
ULONG Reserved2: 1; // 63
|
|||
|
|
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
} SABLE_BCACHE_BCUEA_CSR4, *PSABLE_BCACHE_BCUEA_CSR4;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the memory module CSRs
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef struct _SGL_MEM_CSR0 {
|
|||
|
|
union {
|
|||
|
|
ULONG ErrorSummary1: 1; // 0
|
|||
|
|
ULONG SyncError1: 1; // 1
|
|||
|
|
ULONG CAParityError1: 1; // 2
|
|||
|
|
ULONG CAMissedParityError1: 1; // 3
|
|||
|
|
ULONG WriteParityError1: 1; // 4
|
|||
|
|
ULONG MissedWriteParityError1: 1; // 5
|
|||
|
|
ULONG Reserved1: 2; // 6-7
|
|||
|
|
|
|||
|
|
ULONG CAParityErrorLW0: 1; // 8
|
|||
|
|
ULONG CAParityErrorLW2: 1; // 9
|
|||
|
|
ULONG ParityErrorLW0: 1; // 10
|
|||
|
|
ULONG ParityErrorLW2: 1; // 11
|
|||
|
|
ULONG ParityErrorLW4: 1; // 12
|
|||
|
|
ULONG ParityErrorLW6: 1; // 13
|
|||
|
|
ULONG Reserved2: 2; // 14-15
|
|||
|
|
|
|||
|
|
ULONG EDCUncorrectable1: 1; // 16
|
|||
|
|
ULONG EDCMissedUncorrectable1: 1; // 17
|
|||
|
|
ULONG EDCCorrectable1: 1; // 18
|
|||
|
|
ULONG EDCMissdedCorrectable1: 1; // 19
|
|||
|
|
ULONG Reserved3: 12; // 20-31
|
|||
|
|
|
|||
|
|
ULONG ErrorSummary2: 1; // 32
|
|||
|
|
ULONG SyncError2: 1; // 33
|
|||
|
|
ULONG CAParityError2: 1; // 34
|
|||
|
|
ULONG CAMissedParityError2: 1; // 35
|
|||
|
|
ULONG WriteParityError2: 1; // 36
|
|||
|
|
ULONG MissedWriteParityError2: 1; // 37
|
|||
|
|
ULONG Reserved4: 2; // 38-39
|
|||
|
|
|
|||
|
|
ULONG CAParityErrorLW1: 1; // 40
|
|||
|
|
ULONG CAParityErrorLW3: 1; // 41
|
|||
|
|
ULONG ParityErrorLW1: 1; // 42
|
|||
|
|
ULONG ParityErrorLW3: 1; // 43
|
|||
|
|
ULONG ParityErrorLW5: 1; // 44
|
|||
|
|
ULONG ParityErrorLW7: 1; // 45
|
|||
|
|
ULONG Reserved5: 2; // 46-47
|
|||
|
|
|
|||
|
|
ULONG EDCUncorrectable2: 1; // 48
|
|||
|
|
ULONG EDCMissedUncorrectable2: 1; // 49
|
|||
|
|
ULONG EDCCorrectable2: 1; // 50
|
|||
|
|
ULONG EDCMissdedCorrectable2: 1; // 51
|
|||
|
|
ULONG Reserved6: 12; // 52-63
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
|
|||
|
|
} SGL_MEM_CSR0, *PSGL_MEM_CSR0;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the Interprocessor Interrupt Request Register.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef union _SABLE_IPIR_CSR{
|
|||
|
|
struct{
|
|||
|
|
ULONG RequestInterrupt: 1;
|
|||
|
|
ULONG Reserved0: 31;
|
|||
|
|
ULONG Undefined: 1;
|
|||
|
|
ULONG Reserved1: 2;
|
|||
|
|
ULONG RequestNodeHaltInterrupt: 1;
|
|||
|
|
ULONG Reserved2: 28;
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
} SABLE_IPIR_CSR, *PSABLE_IPIR_CSR;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the System Interrupt Clear Register format.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef union _SABLE_SIC_CSR{
|
|||
|
|
struct{
|
|||
|
|
ULONG Undefined1: 1;
|
|||
|
|
ULONG Undefined2: 1;
|
|||
|
|
ULONG SystemBusErrorInterruptClear: 1;
|
|||
|
|
ULONG Undefined3: 1;
|
|||
|
|
ULONG Reserved1: 28;
|
|||
|
|
ULONG IntervalTimerInterruptClear: 1;
|
|||
|
|
ULONG SystemEventClear: 1;
|
|||
|
|
ULONG Undefinded4: 1;
|
|||
|
|
ULONG NodeHaltInterruptClear: 1;
|
|||
|
|
ULONG Reserved2: 28;
|
|||
|
|
};
|
|||
|
|
ULONGLONG all;
|
|||
|
|
} SABLE_SIC_CSR, *PSABLE_SIC_CSR;
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define the per-processor data structures allocated in the PCR
|
|||
|
|
// for each Sable processor.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
typedef struct _SABLE_PCR{
|
|||
|
|
ULONGLONG HalpCycleCount; // 64-bit per-processor cycle count
|
|||
|
|
EV4ProfileCount ProfileCount; // Profile counter state, do not move
|
|||
|
|
ULONGLONG IpirSva; // Superpage Va of per-processor IPIR CSR
|
|||
|
|
PVOID CpuCsrsQva; // Qva of per-cpu csrs
|
|||
|
|
EV4IrqStatus IrqStatusTable[MaximumIrq]; // Irq status table
|
|||
|
|
} SABLE_PCR, *PSABLE_PCR;
|
|||
|
|
|
|||
|
|
#define HAL_PCR ( (PSABLE_PCR)(&(PCR->HalReserved)) )
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Define Miscellaneous Sable routines.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
WRITE_CPU_REGISTER(
|
|||
|
|
PVOID,
|
|||
|
|
ULONGLONG
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
ULONGLONG
|
|||
|
|
READ_CPU_REGISTER(
|
|||
|
|
PVOID
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
ULONGLONG
|
|||
|
|
READ_MEM_REGISTER(
|
|||
|
|
PVOID
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
VOID
|
|||
|
|
HalpSableIpiInterrupt(
|
|||
|
|
VOID
|
|||
|
|
);
|
|||
|
|
|
|||
|
|
#endif //!_LANGUAGE_ASSEMBLY
|
|||
|
|
|
|||
|
|
#endif //_SABLEH_
|