162 lines
3.8 KiB
C
162 lines
3.8 KiB
C
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/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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isr.c
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Abstract:
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This module contains code for the interrupt service routine
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for the Jazz Sound device driver.
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Author:
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Robin Speed (robinsp) 20-March-1992
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Environment:
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Kernel mode
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Revision History:
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Sameer Dekate (sameer@mips.com) 19-Aug-1992
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- Changes to support the MIPS sound board
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--*/
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#include "sound.h"
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//
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// Driver ISR
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//
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// When we get here, we acknowledge the interrupt from the
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// MIPSSND and simply let the defered processing routine take over
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// to complete the task.
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//
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BOOLEAN
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SoundISR(
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IN PKINTERRUPT pInterrupt,
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IN PVOID Context
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)
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/*++
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Routine Description:
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Interrupt service routine for the MIPS sound card.
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Arguments:
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pInterrupt - our interrupt
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Contest - Pointer to our global device info
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Return Value:
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TRUE if we handled the interrupt
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--*/
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{
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PGLOBAL_DEVICE_INFO pGDI;
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UCHAR configval, endianval, regval ;
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PSOUND_REGISTERS pSoundRegisters;
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pGDI = (PGLOBAL_DEVICE_INFO)Context;
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ASSERT(pGDI->Key == GDI_KEY);
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//
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// Save current Sound state, and then clear the interrupt(s) by writing
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// back the saved value. This works and is safe because the Interrupt bits
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// are "write zero to clear", the enable bit can't be set if DeviceInterrupt
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// bit is set, and the Channel bit can't be changed unless interrupts and
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// the enable bit are clear.
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//
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pSoundRegisters = pGDI->SoundHardware.SoundVirtualBase;
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// Clear the terminal count interrupt, disable interrupts
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endianval = READAUDIO_ENDIAN(&pSoundRegisters);
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WRITEAUDIO_ENDIAN(&pSoundRegisters,
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(endianval & ~(DMA_TCINTR | DMA_TCINTR_ENABLE)));
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// Turn of Overflow and Underflow interrupts
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regval = READAUDIO_DMACNTRL(&pSoundRegisters);
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configval = READAUDIO_CONFIG(&pSoundRegisters);
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WRITEAUDIO_CONFIG(&pSoundRegisters,
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(configval & ~(REC_OVF_INTR | PLAY_UND_INTR)));
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dprintf5("SoundISR:d=0x%x c=0x%x e=0x%x",regval,configval,endianval);
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if (configval & PLAY_UND_INTR) {
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dprintf4("U");
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pGDI->GotUnderFlow = 1;
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// Make sure we stop playing immediately
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WRITEAUDIO_DMACNTRL(&pSoundRegisters, (regval & ~PLAY_ENABLE));
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}
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//
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// If a terminal count interrupt has occured (TcInterrupt), then decrement
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// the pending interrupt count and schedule a Dpc to complete the transfer.
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//
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if ((endianval & DMA_TCINTR) || (configval & PLAY_UND_INTR)) {
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if ((configval & PLAY_UND_INTR) == 0)
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pGDI->SoundHardware.TcInterruptsPending -= 1;
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switch (pGDI->Usage) {
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case SoundInterruptUsageWaveIn:
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dprintf5("i");
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IoRequestDpc(pGDI->pWaveInDevObj,
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pGDI->pWaveInDevObj->CurrentIrp,
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NULL);
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break;
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case SoundInterruptUsageWaveOut:
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dprintf5("o");
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IoRequestDpc(pGDI->pWaveOutDevObj,
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pGDI->pWaveOutDevObj->CurrentIrp,
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NULL);
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break;
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}
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}
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//
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// If DeviceInterrupt (data overflow or underflow), and there are still
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// terminal count interrupts pending, restart controller, else set
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// DeviceBusy flag to false.
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//
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// if (configval & REC_INTR) {
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// if (pGDI->SoundHardware.TcInterruptsPending != 0) {
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// WRITEAUDIO_DMACNTRL(&pSoundRegisters, (regval | REC_ENABLE));
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// }
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// }
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//
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// Re-Enable the interrupts
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//
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WRITEAUDIO_ENDIAN(&pSoundRegisters,
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(endianval & (~DMA_TCINTR | DMA_TCINTR_ENABLE)));
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//
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// Execution continues in the Deferred Procedure Call when it is scheduled
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// Runs SoundInDeferred() or SoundOutDeferred() depending on REC or PLAY
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//
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return TRUE;
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DBG_UNREFERENCED_PARAMETER(pInterrupt);
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}
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