208 lines
7.8 KiB
C
208 lines
7.8 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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dmaregs.h
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Abstract:
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This module defines the offsets of the MCTADR registers to allow
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access to them from assembly code.
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Register names correspond to the ones in the structure DMA_REGISTERS
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declared in jazzdma.h
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Author:
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Lluis Abello 6-May-91
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Revision History:
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Lluis Abello 1-Apr-93 Added DUO registers
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--*/
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#ifndef _DMAREGS
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#define _DMAREGS
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#ifndef DUO
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//
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// DMA REGISTER OFFSETS
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//
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#define DmaConfiguration 0x000
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#define DmaRevisionLevel 0x008
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#define DmaInvalidAddress 0x010
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#define DmaTranslationBase 0x018
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#define DmaTranslationLimit 0x020
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#define DmaTranslationInvalidate 0x028
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#define DmaCacheMaintenance 0x030
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#define DmaRemoteFailedAddress 0x038
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#define DmaMemoryFailedAddress 0x040
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#define DmaPhysicalTag 0x048
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#define DmaLogicalTag 0x050
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#define DmaByteMask 0x058
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#define DmaBufferWindowLow 0x060
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#define DmaBufferWindowHigh 0x068
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#define DmaRemoteSpeed0 0x070
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#define DmaRemoteSpeed1 0x078
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#define DmaRemoteSpeed2 0x080
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#define DmaRemoteSpeed3 0x088
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#define DmaRemoteSpeed4 0x090
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#define DmaRemoteSpeed5 0x098
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#define DmaRemoteSpeed6 0x0a0
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#define DmaRemoteSpeed7 0x0a8
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#define DmaRemoteSpeed8 0x0b0
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#define DmaRemoteSpeed9 0x0b8
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#define DmaRemoteSpeed10 0x0c0
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#define DmaRemoteSpeed11 0x0c8
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#define DmaRemoteSpeed12 0x0d0
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#define DmaRemoteSpeed13 0x0d8
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#define DmaRemoteSpeed14 0x0e0
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#define DmaRemoteSpeed15 0x0e8
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#define DmaParityDiagnosticLow 0x0f0
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#define DmaParityDiagnosticHigh 0x0f8
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#define DmaChannel0Mode 0x100
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#define DmaChannel0Enable 0x108
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#define DmaChannel0ByteCount 0x110
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#define DmaChannel0Address 0x118
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#define DmaChannel1Mode 0x120
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#define DmaChannel1Enable 0x128
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#define DmaChannel1ByteCount 0x130
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#define DmaChannel1Address 0x138
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#define DmaChannel2Mode 0x140
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#define DmaChannel2Enable 0x148
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#define DmaChannel2ByteCount 0x150
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#define DmaChannel2Address 0x158
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#define DmaChannel3Mode 0x160
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#define DmaChannel3Enable 0x168
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#define DmaChannel3ByteCount 0x170
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#define DmaChannel3Address 0x178
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#define DmaChannel4Mode 0x180
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#define DmaChannel4Enable 0x188
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#define DmaChannel4ByteCount 0x190
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#define DmaChannel4Address 0x198
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#define DmaChannel5Mode 0x1a0
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#define DmaChannel5Enable 0x1a8
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#define DmaChannel5ByteCount 0x1b0
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#define DmaChannel5Address 0x1b8
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#define DmaChannel6Mode 0x1c0
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#define DmaChannel6Enable 0x1c8
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#define DmaChannel6ByteCount 0x1d0
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#define DmaChannel6Address 0x1d8
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#define DmaChannel7Mode 0x1e0
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#define DmaChannel7Enable 0x1e8
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#define DmaChannel7ByteCount 0x1f0
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#define DmaChannel7Address 0x1f8
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#define DmaInterruptSource 0x200
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#define DmaErrortype 0x208
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#define DmaRefreshRate 0x210
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#define DmaRefreshCounter 0x218
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#define DmaSystemSecurity 0x220
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#define DmaInterruptInterval 0x228
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#define DmaIntervalTimer 0x230
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#define DmaInterruptAcknowledge 0x238
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#else
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//
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// MP_DMA register offsets for DUO.
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//
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#define DmaConfiguration 0x000
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#define DmaRevisionLevel 0x008
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#define DmaRemoteFailedAddress 0x010
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#define DmaMemoryFailedAddress 0x018
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#define DmaInvalidAddress 0x020
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#define DmaTranslationBase 0x028
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#define DmaTranslationLimit 0x030
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#define DmaTranslationInvalidate 0x038
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#define DmaChannelInterruptAcknowledge 0x040
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#define DmaLocalInterruptAcknowledge 0x048
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#define DmaEisaInterruptAcknowledge 0x050
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#define DmaTimerInterruptAcknowledge 0x058
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#define DmaIpInterruptAcknowledge 0x060
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#define DmaWhoAmI 0x070
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#define DmaNMISource 0x078
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#define DmaRemoteSpeed0 0x080
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#define DmaRemoteSpeed1 0x088
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#define DmaRemoteSpeed2 0x090
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#define DmaRemoteSpeed3 0x098
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#define DmaRemoteSpeed4 0x0A0
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#define DmaRemoteSpeed5 0x0A8
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#define DmaRemoteSpeed6 0x0B0
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#define DmaRemoteSpeed7 0x0B8
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#define DmaRemoteSpeed8 0x0C0
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#define DmaRemoteSpeed9 0x0C8
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#define DmaRemoteSpeed10 0x0D0
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#define DmaRemoteSpeed11 0x0D8
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#define DmaRemoteSpeed12 0x0E0
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#define DmaRemoteSpeed13 0x0E8
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#define DmaRemoteSpeed14 0x0F0
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#define DmaInterruptEnable 0x0F8
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#define DmaChannel0Mode 0x100
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#define DmaChannel0Enable 0x108
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#define DmaChannel0ByteCount 0x110
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#define DmaChannel0Address 0x118
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#define DmaChannel1Mode 0x120
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#define DmaChannel1Enable 0x128
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#define DmaChannel1ByteCount 0x130
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#define DmaChannel1Address 0x138
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#define DmaChannel2Mode 0x140
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#define DmaChannel2Enable 0x148
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#define DmaChannel2ByteCount 0x150
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#define DmaChannel2Address 0x158
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#define DmaChannel3Mode 0x160
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#define DmaChannel3Enable 0x168
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#define DmaChannel3ByteCount 0x170
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#define DmaChannel3Address 0x178
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#define DmaArbitrationControl 0x180
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#define DmaErrortype 0x188
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#define DmaRefreshRate 0x190
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#define DmaRefreshCounter 0x198
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#define DmaSystemSecurity 0x1A0
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#define DmaInterruptInterval 0x1A8
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#define DmaIntervalTimer 0x1B0
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#define DmaIpi 0x1B8
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#define DmaInterruptDiagnostic 0x1C0
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#define DmaEccDiagnostic 0x1C8
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#define DmaMemoryConfig0 0x1D0
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#define DmaMemoryConfig1 0x1D8
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#define DmaMemoryConfig2 0x1E0
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#define DmaMemoryConfig3 0x1E8
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#define IoCacheBufferBase 0x200
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#define DmaIoCachePhysicalTag0 0x400
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#define DmaIoCachePhysicalTag1 0x408
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#define DmaIoCachePhysicalTag2 0x410
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#define DmaIoCachePhysicalTag3 0x418
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#define DmaIoCachePhysicalTag4 0x420
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#define DmaIoCachePhysicalTag5 0x428
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#define DmaIoCachePhysicalTag6 0x430
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#define DmaIoCachePhysicalTag7 0x438
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#define DmaIoCacheLogicalTag0 0x440
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#define DmaIoCacheLogicalTag1 0x448
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#define DmaIoCacheLogicalTag2 0x450
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#define DmaIoCacheLogicalTag3 0x458
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#define DmaIoCacheLogicalTag4 0x460
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#define DmaIoCacheLogicalTag5 0x468
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#define DmaIoCacheLogicalTag6 0x470
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#define DmaIoCacheLogicalTag7 0x478
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#define DmaIoCacheLowByteMask0 0x480
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#define DmaIoCacheLowByteMask1 0x488
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#define DmaIoCacheLowByteMask2 0x490
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#define DmaIoCacheLowByteMask3 0x498
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#define DmaIoCacheLowByteMask4 0x4A0
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#define DmaIoCacheLowByteMask5 0x4A8
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#define DmaIoCacheLowByteMask6 0x4B0
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#define DmaIoCacheLowByteMask7 0x4B8
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#define DmaIoCacheHighByteMask0 0x4C0
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#define DmaIoCacheHighByteMask1 0x4C8
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#define DmaIoCacheHighByteMask2 0x4D0
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#define DmaIoCacheHighByteMask3 0x4D8
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#define DmaIoCacheHighByteMask4 0x4E0
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#define DmaIoCacheHighByteMask5 0x4E8
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#define DmaIoCacheHighByteMask6 0x4F0
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#define DmaIoCacheHighByteMask7 0x4F8
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#endif // DUO
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#endif //_DMAREGS
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