377 lines
11 KiB
C
377 lines
11 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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iodevice.h
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Abstract:
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This module contains definitions to access the
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IO devices in the jazz system.
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Author:
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Lluis Abello (lluis) 03-Jan-1991
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Environment:
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Revision History:
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--*/
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#ifndef _IODEVICE_
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#define _IODEVICE_
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#ifndef DUO
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#include <jazzprom.h>
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#include <jazzdef.h>
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#else
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#include <duoprom.h>
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#include <duodef.h>
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#endif
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#include <jazzserp.h>
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#include <eisa.h> // for the isp interrupt controller init.
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#include <jazzrtc.h>
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#ifndef DUO
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#include <ncr53c94.h>
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#else
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#include <ncrc700.h>
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#define SCSI_READ_UCHAR(ChipAddr,Register) \
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(READ_REGISTER_UCHAR (&((ChipAddr)->Register)))
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#define SCSI_READ_USHORT(ChipAddr,Register) \
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(READ_REGISTER_USHORT (&((ChipAddr)->Register)))
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#define SCSI_READ_ULONG(ChipAddr,Register) \
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(READ_REGISTER_ULONG (&((ChipAddr)->Register)))
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#define SCSI_WRITE_UCHAR(ChipAddr,Register, Value) \
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WRITE_REGISTER_UCHAR(&((ChipAddr)->Register), (Value))
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#define SCSI_WRITE_USHORT(ChipAddr, Register, Value) \
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WRITE_REGISTER_USHORT(&((ChipAddr)->Register), (Value))
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#define SCSI_WRITE_ULONG(ChipAddr, Register, Value) \
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WRITE_REGISTER_ULONG(&((ChipAddr)->Register), (Value))
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#endif
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ARC_STATUS
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FwWaitForDeviceInterrupt(
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USHORT InterruptMask,
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ULONG Timeout
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);
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//
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// COM controller register pointer definitions.
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//
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#define SP1_READ ((volatile PSP_READ_REGISTERS) COMPORT1_VIRTUAL_BASE)
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#define SP1_WRITE ((volatile PSP_WRITE_REGISTERS)COMPORT1_VIRTUAL_BASE)
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#define SP2_READ ((volatile PSP_READ_REGISTERS) COMPORT2_VIRTUAL_BASE)
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#define SP2_WRITE ((volatile PSP_WRITE_REGISTERS)COMPORT2_VIRTUAL_BASE)
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//
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// PARALLEL port write registers.
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//
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typedef struct _PARALLEL_WRITE_REGISTERS {
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UCHAR Data;
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UCHAR Invalid;
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UCHAR Control;
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} PARALLEL_WRITE_REGISTERS, * PPARALLEL_WRITE_REGISTERS;
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//
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// PARALLEL port read Registers
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//
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typedef struct _PARALLEL_READ_REGISTERS {
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UCHAR Data;
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UCHAR Status;
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UCHAR Control;
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} PARALLEL_READ_REGISTERS,* PPARALLEL_READ_REGISTERS;
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//
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// PARALLEL controller register pointer definitions.
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//
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#define PARALLEL_READ ((volatile PPARALLEL_READ_REGISTERS) PARALLEL_VIRTUAL_BASE)
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#define PARALLEL_WRITE ((volatile PPARALLEL_WRITE_REGISTERS)PARALLEL_VIRTUAL_BASE)
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//
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// FLOPPY read registers.
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//
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typedef struct _FLOPPY_READ_REGISTERS {
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UCHAR StatusA;
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UCHAR StatusB;
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UCHAR DigitalOutput;
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UCHAR Reserved1;
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UCHAR MainStatus;
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UCHAR Fifo;
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UCHAR Reserved2;
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UCHAR DigitalInput;
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} FLOPPY_READ_REGISTERS, * PFLOPPY_READ_REGISTERS;
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//
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// FLOPPY write registers.
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//
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typedef struct _FLOPPY_WRITE_REGISTERS {
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UCHAR StatusA;
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UCHAR StatusB;
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UCHAR DigitalOutput;
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UCHAR Reserved1;
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UCHAR DataRateSelect;
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UCHAR Fifo;
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UCHAR Reserved2;
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UCHAR ConfigurationControl;
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} FLOPPY_WRITE_REGISTERS, * PFLOPPY_WRITE_REGISTERS ;
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//
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// FLOPPY controller register pointer definitions.
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//
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#define FLOPPY_READ ((volatile PFLOPPY_READ_REGISTERS)FLOPPY_VIRTUAL_BASE)
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#define FLOPPY_WRITE ((volatile PFLOPPY_WRITE_REGISTERS)FLOPPY_VIRTUAL_BASE)
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//
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// SOUND controller register pointer definitions.
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//
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typedef struct _SOUND_REGISTERS {
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USHORT Control;
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USHORT Mode;
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} SOUND_REGISTERS,* PSOUND_REGISTERS;
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typedef struct _SOUND_CONTROL {
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USHORT SoundEnable : 1;
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USHORT Direction : 1;
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USHORT ChannelInUse : 1;
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USHORT Reserved1 : 11;
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USHORT TerminalCountInterrupt : 1;
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USHORT DeviceInterrupt : 1;
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} SOUND_CONTROL, *PSOUND_CONTROL;
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#define DIRECTION_ACQUISITION 0
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#define DIRECTION_PLAYBACK 1
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#define CHANNEL2_IN_USE 0
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#define CHANNEL3_IN_USE 1
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typedef struct _SOUND_MODE {
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USHORT Frequency : 2;
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USHORT Reserved1 : 1;
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USHORT Resolution : 1;
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USHORT Reserved2 : 1;
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USHORT NumberOfChannels : 1;
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USHORT Reserved3 : 10;
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} SOUND_MODE, *PSOUND_MODE;
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#define CHANNEL_MONO 0
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#define CHANNEL_STEREO 1
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#define RESOLUTION_16BIT 1
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#define RESOLUTION_8BIT 0
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#define FREQUENCY_11KHZ 0
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#define FREQUENCY_22KHZ 1
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#define FREQUENCY_44KHZ 2
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#define FREQUENCY_DISABLED 3
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#define SOUND_CONTROL ((volatile PSOUND_REGISTERS) SOUND_VIRTUAL_BASE)
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//
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// cursor controller register pointer definitions.
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//
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#define CURSOR_CONTROLLER ((volatile PCURSOR_REGISTERS) (VIDEO_CURSOR_VIRTUAL_BASE))
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#define VIDEO_CONTROLLER ((volatile PVIDEO_REGISTERS) (VIDEO_CONTROL_VIRTUAL_BASE))
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//
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// KEYBOARD write registers.
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//
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typedef struct _KEYBOARD_WRITE_REGISTERS {
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UCHAR Data;
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UCHAR Command;
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} KEYBOARD_WRITE_REGISTERS, * PKEYBOARD_WRITE_REGISTERS;
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//
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// KEYBOARD read Registers
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//
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typedef struct _KEYBOARD_READ_REGISTERS {
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UCHAR Data;
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UCHAR Status;
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} KEYBOARD_READ_REGISTERS, * PKEYBOARD_READ_REGISTERS;
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//
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// KEYBOARD controller register pointer definitions.
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//
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#define KEYBOARD_READ ((volatile PKEYBOARD_READ_REGISTERS) KEYBOARD_VIRTUAL_BASE)
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#define KEYBOARD_WRITE ((volatile PKEYBOARD_WRITE_REGISTERS) KEYBOARD_VIRTUAL_BASE)
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//
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// Keyboard circular buffer type definition.
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//
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#define KBD_BUFFER_SIZE 32
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typedef struct _KEYBOARD_BUFFER {
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volatile UCHAR Buffer[KBD_BUFFER_SIZE];
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volatile UCHAR ReadIndex;
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volatile UCHAR WriteIndex;
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} KEYBOARD_BUFFER, *PKEYBOARD_BUFFER;
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#define TIME_OUT 0xdead
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//
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// SONIC registers definition.
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//
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typedef struct _SONIC_REGISTER { // Structure to align the registers
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USHORT Reg;
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USHORT Fill;
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} SONIC_REGISTER;
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typedef struct _SONIC_REGISTERS {
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SONIC_REGISTER Command; // 0
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SONIC_REGISTER DataConfiguration; // 1
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SONIC_REGISTER ReceiveControl; // 2
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SONIC_REGISTER TransmitControl; // 3
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SONIC_REGISTER InterruptMask; // 4
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SONIC_REGISTER InterruptStatus; // 5
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SONIC_REGISTER UTDA; // 6
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SONIC_REGISTER CTDA; // 7
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SONIC_REGISTER InternalTPS; // 8
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SONIC_REGISTER InternalTFC; // 9
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SONIC_REGISTER InternalTSA0; // A
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SONIC_REGISTER InternalTSA1; // B
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SONIC_REGISTER InternalTFS; // C
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SONIC_REGISTER URDA; // D
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SONIC_REGISTER CRDA; // E
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SONIC_REGISTER InternalCRBA0; // F
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SONIC_REGISTER InternalCRBA1; //10
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SONIC_REGISTER InternalRWBC0; //11
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SONIC_REGISTER InternalRBWC1; //12
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SONIC_REGISTER EOBC; //13
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SONIC_REGISTER URRA; //14
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SONIC_REGISTER RSA; //15
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SONIC_REGISTER REA; //16
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SONIC_REGISTER RRP; //17
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SONIC_REGISTER RWP; //18
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SONIC_REGISTER InternalTRBA0; //19
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SONIC_REGISTER InternalTRBA1; //1A
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SONIC_REGISTER InternalTBWC0; //1B
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SONIC_REGISTER InternalTBWC1; //1C
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SONIC_REGISTER InternalADDR0; //1D
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SONIC_REGISTER InternalADDR1; //1E
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SONIC_REGISTER InternalLLFA; //1F
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SONIC_REGISTER InternalTTDA; //20
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SONIC_REGISTER CamEntryPtr; //21
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SONIC_REGISTER CamAddrPort2; //22
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SONIC_REGISTER CamAddrPort1; //23
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SONIC_REGISTER CamAddrPort0; //24
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SONIC_REGISTER CamEnable; //25
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SONIC_REGISTER CamDscrPtr; //26
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SONIC_REGISTER CamDscrCount; //27
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SONIC_REGISTER SiliconRevision; //28
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SONIC_REGISTER WatchdogTimer0; //29
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SONIC_REGISTER WatchdogTimer1; //2A
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SONIC_REGISTER ReceiveSequenceCounter; //2B
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SONIC_REGISTER CrcErrorTally; //2C
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SONIC_REGISTER FaeTally; //2D
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SONIC_REGISTER MissedPacketTally; //2E
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SONIC_REGISTER InternalMDT; //2F
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// registers 30 to 3F are Test registers and must not be accessed
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// registers nammed "internal" must not be accessed either.
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} SONIC_REGISTERS, * PSONIC_REGISTERS;
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//
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// SONIC register pointer definitions.
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//
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#define SONIC ((volatile PSONIC_REGISTERS) NET_VIRTUAL_BASE)
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//
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// NVRAM address definitions.
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//
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#define NVRAM_PAGE0 NVRAM_VIRTUAL_BASE
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#define NVRAM_PAGE1 (NVRAM_VIRTUAL_BASE+0x1000)
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#define NVRAM_PAGE2 (NVRAM_VIRTUAL_BASE+0x2000)
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#define READ_ONLY_DISABLE_WRITE 0x6 // clear lower bit of Security register.
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//
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// EISA Stuff
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// ***** temp **** this should be replaced by the definition in
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// "ntos\inc\eisa.h" as soon as it is complete.
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//
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typedef struct _EISA {
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UCHAR Dma1Ch0Address; //0x00
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UCHAR Dma1Ch0Count; //0x01
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UCHAR Dma1Ch1Address; //0x02
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UCHAR Dma1Ch1Count; //0x03
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UCHAR Dma1Ch2Address; //0x04
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UCHAR Dma1Ch2Count; //0x05
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UCHAR Dma1Ch3Address; //0x06
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UCHAR Dma1Ch3Count; //0x07
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UCHAR Dma1StatusCommand; //0x08
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UCHAR Dma1Request; //0x09
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UCHAR Dma1SingleMask; //0x0a
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UCHAR Dma1Mode; //0x0b
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UCHAR Dma1ClearBytePointer; //0x0c
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UCHAR Dma1MasterClear; //0x0d
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UCHAR Dma1ClearMask; //0x0e
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UCHAR Dma1AllMask; //0x0f
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ULONG Fill01; //0x10-13
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ULONG Fill02; //0x14-17
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ULONG Fill03; //0x18-1b
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ULONG Fill04; //0x1c-1f
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UCHAR Int1Control; //0x20
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UCHAR Int1Mask; //0x21
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USHORT Fill10; //0x22-23
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ULONG Fill11; //0x24
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ULONG Fill12; //0x28
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ULONG Fill13; //0x2c
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ULONG Fill14; //0x30
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ULONG Fill15; //0x34
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ULONG Fill16; //0x38
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ULONG Fill17; //0x3c
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UCHAR IntTimer1SystemClock; //0x40
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UCHAR IntTimer1RefreshRequest; //0x41
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UCHAR IntTimer1SpeakerTone; //0x42
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UCHAR IntTimer1CommandMode; //0x43
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ULONG Fill20; //0x44
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UCHAR IntTimer2FailsafeClock; //0x48
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UCHAR IntTimer2Reserved; //0x49
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UCHAR IntTimer2CPUSpeeedCtrl; //0x4a
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UCHAR IntTimer2CommandMode; //0x4b
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ULONG Fill30; //0x4c
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ULONG Fill31; //0x50
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ULONG Fill32; //0x54
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ULONG Fill33; //0x58
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ULONG Fill34; //0x5c
|
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|
UCHAR Fill35; //0x60
|
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|
UCHAR NMIStatus; //0x61
|
|||
|
|
UCHAR Fill40; //0x62
|
|||
|
|
UCHAR Fill41; //0x63
|
|||
|
|
ULONG Fill42; //0x64
|
|||
|
|
ULONG Fill43; //0x68
|
|||
|
|
ULONG Fill44; //0x6c
|
|||
|
|
UCHAR NMIEnable; //0x70
|
|||
|
|
}EISA, * PEISA;
|
|||
|
|
|
|||
|
|
#define ISP ((volatile PEISA) EISA_IO_VIRTUAL_BASE)
|
|||
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|
|
|||
|
|
#define EISA_CONTROL ((volatile PEISA_CONTROL) EISA_IO_VIRTUAL_BASE)
|
|||
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|
|||
|
|
#endif // _IODEVICE_
|
|||
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|
|
|||
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