247 lines
7.2 KiB
C
247 lines
7.2 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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sonictst.h
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Abstract:
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This module contains the define constants for the SONIC ethernet controller
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selftest in the jazz system.
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Author:
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Lluis Abello (lluis) 19-Feb-1991
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Environment:
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Revision History:
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--*/
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#define LAN_MEMORY_ERROR 1
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#define LAN_ADDRESS_ERROR 2
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//
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// Transmit Control Register bit definitions
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//
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#define TCR_PTX (1 << 0)
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#define TCR_BCM (1 << 1)
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#define TCR_FU (1 << 2)
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#define TCR_PMB (1 << 3)
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#define TCR_OWC (1 << 5)
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#define TCR_EXC (1 << 6)
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#define TCR_CRSL (1 << 7)
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#define TCR_NCRS (1 << 8)
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#define TCR_DEF (1 << 9)
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#define TCR_EXD (1 << 10)
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#define TCR_EXDIS (1 << 12)
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#define TCR_CRCI (1 << 13)
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#define TCR_POWC (1 << 14)
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#define TCR_PINT (1 << 15)
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//
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// Receive Control Register
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//
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#define RCR_PRX (1 << 0) // Packet recived OK
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#define RCR_LBK (1 << 1) // Loopback packet received.
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#define RCR_FAER (1 << 2) // Frame alignament error.
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#define RCR_CRCR (1 << 3) // CRC Error
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#define RCR_COL (1 << 4) // Collision activity
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#define RCR_CRS (1 << 5) // Carrier sense activity
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#define RCR_LPKT (1 << 6) // Last packet in RBA
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#define RCR_BC (1 << 7) // Broadcast packet received
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#define RCR_MC (1 << 8) // Multicast packet received
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#define RCR_MAC (1 << 9) // MAC Loopback
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#define RCR_ENDEC (1 <<10) // ENDEC loopback
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#define RCR_TRANS (3 << 9) // Transceiver loopback
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#define RCR_AMC (1 <<11) // Accept all musticast packets
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#define RCR_PRO (1 <<12) // Physical promiscuious packets
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#define RCR_BRD (1 <<13) // Accept Broadcast packets
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#define RCR_RNT (1 <<14) // Accept Runt packets
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#define RCR_ERR (1 <<15) // Accept Packets with errors
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//
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// Data configuration register value.
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//
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#define DATA_CONFIGURATION 0x2439 // 0x2439
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//
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// Interrupt Mask Register and Interrupt Status Register bit definitions
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//
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#define INT_RFO (1 << 0) // receive fifo overrun
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#define INT_MP (1 << 1) // Missed Packed counter rollover
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#define INT_FAE (1 << 2) // Frame alignment error
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#define INT_CRC (1 << 3) // CRC tally counter rollover
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#define INT_RBAE (1 << 4) // Receive Buffer Area exceded
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#define INT_RBE (1 << 5) // Recive Buffers exhausted
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#define INT_RDE (1 << 6) // Recive descriptors exhausted
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#define INT_TC (1 << 7) // Timer complete
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#define INT_TXER (1 << 8) // Transmit error
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#define INT_TXDN (1 << 9) // Transmission done
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#define INT_PKTRX (1 << 10) // Packet received
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#define INT_PINT (1 << 11) // Programable interrupt
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#define INT_LCD (1 << 12) // Load CAM done.
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#define INT_HBL (1 << 13) // CD heartbeat lost
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#define INT_BR (1 << 14) // Bus retry
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//
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// Command register bit definitions.
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//
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#define CR_HTX (1 << 0) // Halt Transmission
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#define CR_TXP (1 << 1) // Transmit packets
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#define CR_RXDIS (1 << 2) // Receiver disable
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#define CR_RXEN (1 << 3) // receiver enable
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#define CR_STP (1 << 4) // stop timer
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#define CR_ST (1 << 5) // start timer
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#define CR_RST (1 << 7) // software reset
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#define CR_RRA (1 << 8) // read RRA
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#define CR_LCAM (1 << 9) // load CAM
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//
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// Resurce & Data tables structure definition.
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//
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typedef struct _SONIC_ENTRY {
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USHORT Data; // all tables in memory
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USHORT Fill; // trash the upper 16 bits
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} SONIC_ENTRY;
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//
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// Receive Resource Area Format definition
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//
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typedef struct _RECEIVE_RESOURCE {
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SONIC_ENTRY BufferPtr0;
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SONIC_ENTRY BufferPtr1;
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SONIC_ENTRY WordCount0;
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SONIC_ENTRY WordCount1;
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} RECEIVE_RESOURCE, * PRECEIVE_RESOURCE;
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//
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// Declare a variable that will point to the resource descriptor area.
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//
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PRECEIVE_RESOURCE ReceivePhysRsrc;
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PRECEIVE_RESOURCE ReceiveLogRsrc;
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//
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// Offset between physical and logical Receive Buffers to allow an easy
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// translation from logical to physical pointers to received packets.
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//
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ULONG ReceiveBufferTranslationOffset;
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#define RBA_SIZE 0x1000
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//
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// CAM_DESCRIPTOR format definition
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//
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typedef struct _CAM_DESCRIPTOR {
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SONIC_ENTRY EntryPointer;
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SONIC_ENTRY Port0;
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SONIC_ENTRY Port1;
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SONIC_ENTRY Port2;
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} CAM_DESCRIPTOR;
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typedef CAM_DESCRIPTOR * PCAM_DESCRIPTOR;
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PCAM_DESCRIPTOR PhysCamDescriptor,LogCamDescriptor;
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//
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// Receive Descriptor Format definition.
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//
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typedef struct _RECEIVE_DESCRIPTOR {
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SONIC_ENTRY Status;
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SONIC_ENTRY ByteCount;
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SONIC_ENTRY PktPtr0;
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SONIC_ENTRY PktPtr1;
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SONIC_ENTRY SeqNo;
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SONIC_ENTRY Link;
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SONIC_ENTRY InUse;
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} RECEIVE_DESCRIPTOR;
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typedef RECEIVE_DESCRIPTOR * PRECEIVE_DESCRIPTOR;
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//
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// Receive Descriptor Field value definitions
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//
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#define AVAILABLE 0xFABA // Descriptor Available to SONIC
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#define IN_USE 0 // Descriptor being used by SONIC
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#define EOL 1 // To be ORed with the Link field to make the
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// descriptor become the last one of the list
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#define NOT_EOL 0xFFFE // To be ANDed with the Link field to make the
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// descriptor not be the last one of the list
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typedef struct _RECEIVE_DESCRIPTOR_QUEUE {
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PRECEIVE_DESCRIPTOR Base;
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ULONG Current;
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ULONG Last;
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} RECEIVE_DESCRIPTOR_QUEUE;
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RECEIVE_DESCRIPTOR_QUEUE ReceiveDscrQueue;
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#define CURRENT_DESCRIPTOR ((PRECEIVE_DESCRIPTOR)((ULONG) ReceiveDscrQueue.Base | ReceiveDscrQueue.Current))
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#define LAST_DESCRIPTOR ((PRECEIVE_DESCRIPTOR)((ULONG) ReceiveDscrQueue.Base | ReceiveDscrQueue.Last))
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//
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// Transmit Descriptor definition
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//
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typedef struct _TRANSMIT_DESCRIPTOR {
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SONIC_ENTRY Status;
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SONIC_ENTRY Config;
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SONIC_ENTRY PktSize;
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SONIC_ENTRY FragCount; // Must be 1. We don't need to scater
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SONIC_ENTRY FragPtr0; // the paket in memory and this let's us define
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SONIC_ENTRY FragPtr1; // a fixed size structure with only one pointer
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SONIC_ENTRY FragSize; // and one size field per paket.
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SONIC_ENTRY Link;
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} TRANSMIT_DESCRIPTOR;
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typedef TRANSMIT_DESCRIPTOR * PTRANSMIT_DESCRIPTOR;
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PTRANSMIT_DESCRIPTOR PhysTransmitDscr;
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PTRANSMIT_DESCRIPTOR LogicalTransmitDscr;
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typedef struct _SONIC_DATA {
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USHORT InterruptID;
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USHORT ExpectedInt;
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USHORT TransmitControl;
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USHORT Status;
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} SONIC_DATA,* PSONIC_DATA;
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volatile SONIC_DATA SonicStatus;
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//
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// Define status.
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//
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#define ERROR 1
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#define DONE 0
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//
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// Macro definition
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//
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#define EXPECTED_INT (InterruptStatus & SonicStatus.ExpectedInt)
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#define NO_OTHER_INT ((InterruptStatus & (~SonicStatus.ExpectedInt))==0)
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#define MAX_PACKET_SIZE 1520
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#define MAX_DATA_LENGTH 1500
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#define MIN_DATA_LENGTH 46
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//
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// Resources Logical & Physical addresses.
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//
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#define PHYS_RECEIVE_DSCR_ADDRESS 0xA0100000 // the lower 16 bits of both
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#define LOGICAL_RECEIVE_DSCR_ADDRESS 0x00000000 // Log & Phys add must match.
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#define RECEIVE_PHYS_RSRC_ADDRESS 0xA0101000
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#define RECEIVE_LOG_RSRC_ADDRESS 0x00001000
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#define RECEIVE_PHYS_BUFFER_ADDRESS 0xA0102000
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#define RECEIVE_LOG_BUFFER_ADDRESS 0x00002000
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#define PHYS_TRANSMIT_DSCR_ADDRESS 0xA0104000
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#define LOGICAL_TRANSMIT_DSCR_ADDRESS 0x00004000
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#define PHYS_TBA_ADDRESS 0xA0105000
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#define LOG_TBA_ADDRESS 0x00005000
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volatile ULONG SonicIntSemaphore;
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extern UCHAR StationAddress[6];
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ULONG SonicErrors;
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