413 lines
9.8 KiB
C
413 lines
9.8 KiB
C
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/*++
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Copyright (c) 1991-4 Microsoft Corporation
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Module Name:
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cpqarray.h
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Abstract:
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This file contains definitions of structures used to
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communicate with the Compaq Intelligent Disk Array.
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Author:
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Mike Glass (mglass)
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Tom Bonola (Compaq)
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Notes:
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Revision History:
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--*/
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//
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// The Command List Header contiains information that applies to all
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// the Request Blocks in the Command List.
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//
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typedef struct _COMMAND_LIST_HEADER {
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UCHAR LogicalDriveNumber;
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UCHAR RequestPriority;
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USHORT Flags;
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} COMMAND_LIST_HEADER, *PCOMMAND_LIST_HEADER;
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//
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// Request Priorities
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//
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#define CL_NORMAL_PRIORITY 0x02
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//
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// Flag word bit definitions
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//
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#define CL_FLAGS_NOTIFY_LIST_COMPLETE 0x0000
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#define CL_FLAGS_NOTIFY_REQUEST_COMPLETE 0x0001
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#define CL_FLAGS_NOTIFY_LIST_ERROR 0x0000
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#define CL_FLAGS_NOTIFY_REQUEST_ERROR 0x0002
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#define CL_FLAGS_ABORT_ON_ERROR 0x0004
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#define CL_FLAGS_ORDERED_REQUESTS 0x0008
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typedef struct _REQUEST_HEADER {
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USHORT NextRequestOffset;
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UCHAR CommandByte;
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UCHAR ErrorCode;
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ULONG BlockNumber;
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USHORT BlockCount;
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UCHAR ScatterGatherCount;
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UCHAR Reserved;
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} REQUEST_HEADER, *PREQUEST_HEADER;
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//
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// Error code definitions
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//
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#define RH_SUCCESS 0x00
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#define RH_INVALID_REQUEST 0x10
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#define RH_REQUEST_ABORTED 0x08
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#define RH_FATAL_ERROR 0x04
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#define RH_RECOVERABLE_ERROR 0x02
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#define RH_WARNING 0x40
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#define RH_BAD_COMMAND_LIST 0x20
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//
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// Scatter/Gather descriptor definition
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//
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#define PAGE_SIZE (ULONG)0x1000
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#define MAXIMUM_SG_DESCRIPTORS 17
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#define MAXIMUM_TRANSFER_SIZE (MAXIMUM_SG_DESCRIPTORS - 1) * PAGE_SIZE
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typedef struct _SG_DESCRIPTOR {
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ULONG Length;
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ULONG Address;
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} SG_DESCRIPTOR, *PSG_DESCRIPTOR;
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//
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// Command List
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//
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typedef struct _COMMAND_LIST {
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//
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// Compaq RLH.
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//
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COMMAND_LIST_HEADER CommandListHeader;
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REQUEST_HEADER RequestHeader;
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SG_DESCRIPTOR SgDescriptor[MAXIMUM_SG_DESCRIPTORS];
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//
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// Next list entry
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//
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struct _COMMAND_LIST *NextEntry;
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//
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// SRB pointer
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//
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PSCSI_REQUEST_BLOCK SrbAddress;
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//
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// Request tracking flags
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//
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ULONG Flags;
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//
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// Command list size.
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//
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USHORT CommandListSize;
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} COMMAND_LIST, *PCOMMAND_LIST;
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//
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// Commands
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//
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#define RH_COMMAND_IDENTIFY_LOGICAL_DRIVES 0x10
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#define RH_COMMAND_IDENTIFY_CONTROLLER 0x11
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#define RH_COMMAND_IDENTIFY_LOGICAL_DRIVE_STATUS 0x12
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#define RH_COMMAND_READ 0x20
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#define RH_COMMAND_WRITE 0x30
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#define RH_COMMAND_SENSE_CONFIGURATION 0x50
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#define RH_COMMAND_SET_CONFIGURATION 0x51
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#define RH_COMMAND_FLUSH_DISABLE_CACHE 0xc2
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#define RH_COMMAND_SCSI_PASS_THRU 0x90
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//
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// Flag field bit definitions
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//
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#define CL_FLAGS_REQUEST_QUEUED 0x0001
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#define CL_FLAGS_REQUEST_STARTED 0x0002
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#define CL_FLAGS_REQUEST_COMPLETED 0x0004
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#define CL_FLAGS_IDENTIFY_REQUEST 0x0008
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//
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// Fixed Disk Parameter Table
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//
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#pragma pack(1)
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typedef struct _DISK_PARAMETER_TABLE {
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USHORT MaximumCylinders; // BIOS translated
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UCHAR MaximumHeads; // BIOS translated
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UCHAR TranslationSignature;
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UCHAR SectorsPerTrack; // physical characteristics
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USHORT WritePrecompCylinder;
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UCHAR MaximumECCBurst;
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UCHAR DriveControl;
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USHORT NumberOfCylinders; // physical characteristics
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UCHAR NumberOfHeads; // physical characteristics
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USHORT LandingZone;
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UCHAR MaximumSectorsPerTrack; // BIOS translated
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UCHAR CheckSum;
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} DISK_PARAMETER_TABLE, *PDISK_PARAMETER_TABLE;
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#define IDENTIFY_BUFFER_SIZE 512
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//
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// Identify Logical Drives
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//
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typedef struct _IDENTIFY_LOGICAL_DRIVE {
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USHORT BlockLength;
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ULONG NumberOfBlocks;
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DISK_PARAMETER_TABLE ParameterTable;
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UCHAR FaultToleranceType;
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UCHAR Reserved[5];
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} IDENTIFY_LOGICAL_DRIVE, *PIDENTIFY_LOGICAL_DRIVE;
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//
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// Identify Controller information
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//
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typedef struct _IDENTIFY_CONTROLLER {
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UCHAR NumberLogicalDrives;
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ULONG ConfigurationSignature;
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UCHAR FirmwareRevision[4];
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UCHAR Reserved[247];
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} IDENTIFY_CONTROLLER, *PIDENTIFY_CONTROLLER;
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//
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// Set/Sense Configuration information
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//
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typedef struct _SENSE_CONFIGURATION {
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ULONG ConfigurationSignature;
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USHORT SiConfiguration;
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USHORT OsConfiguration;
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USHORT NumberPhysicalDrives;
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USHORT PDrivesInLDrives;
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USHORT FaultToleranceType;
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UCHAR PhysicalDrive[16];
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UCHAR LogicalDrive[16];
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ULONG DriveAssignmentMap;
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UCHAR Reserved[462];
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} SENSE_CONFIGURATION, *PCONFIGURATION;
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//
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// Fault Tolerance Type
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//
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#define FT_DATA_GUARD 0x0002
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#define FT_MIRRORING 0x0001
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#define FT_NONE_ 0x0000
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//
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// Drive Failure Assignment Map
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//
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typedef struct _DRIVE_FAILURE_MAP {
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UCHAR LogicalDriveStatus;
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UCHAR DriveFailureAssignmentMap[4];
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UCHAR Reserved[251];
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} DRIVE_FAILURE_MAP, *PDRIVE_FAILURE_MAP;
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#pragma pack()
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typedef struct _MAILBOX {
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ULONG Address;
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USHORT Length;
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UCHAR Status;
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UCHAR TagId;
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} MAILBOX, *PMAILBOX;
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//
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// Command List Status bit definitions
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//
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#define CL_STATUS_LIST_COMPLETE 0x01
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#define CL_STATUS_NONFATAL_ERROR 0x02
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#define CL_STATUS_FATAL_ERROR 0x04
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#define CL_STATUS_ABORT 0x08
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//
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// 32-bit IDA Controller registers
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//
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typedef struct _IDA_CONTROLLER {
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ULONG BoardId; // xC80
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UCHAR Undefined[4]; // xC84
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UCHAR Configuration; // xC88
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UCHAR InterruptControl; // xC89
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UCHAR Undefined1[2]; // xC8A
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UCHAR LocalDoorBellMask; // xC8C
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UCHAR LocalDoorBell; // xC8D
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UCHAR SystemDoorBellMask; // xC8E
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UCHAR SystemDoorBell; // xC8F
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MAILBOX CommandListSubmit; // xC90
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MAILBOX CommandListComplete; // xC98`
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UCHAR Reserved[32]; // xCA0
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UCHAR ControllerConfiguration; // xCC0
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} IDA_CONTROLLER, *PIDA_CONTROLLER;
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//
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// Controller bHBAModel definitions
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//
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#define IDA_UNDEFINED_CONTROLLER 0
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#define IDA_BASE_CONTROLLER 1
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#define IDA_PCI_DAZZLER 2
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#define IDA_EISA_DAZZLER 3
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//
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// DAZZLER PCI interface definitions for EISA I/O space
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//
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typedef struct _EISAPCI_CONTROLLER {
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ULONG Timer; // x000
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ULONG CPFIFO; // x004
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ULONG CCFIFO; // x008
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ULONG InterruptMask; // x00C
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ULONG InterruptStatus; // x010
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ULONG InterruptPending; // x014
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} EISAPCI_CONTROLLER, *PEISAPCI_CONTROLLER;
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#define IDA_PCI_TIMER_OFFSET 0
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#define IDA_PCI_CPFIFO_OFFSET 4
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#define IDA_PCI_CCFIFO_OFFSET 8
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#define IDA_PCI_MASK_OFFSET 12
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#define IDA_PCI_STATUS_OFFSET 16
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#define IDA_PCI_PENDING_OFFSET 20
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#define IDA_PCI_IRQ_DISABLE_MASK 0x00000000
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#define IDA_PCI_FIFO_NOT_EMPTY_MASK 0x00000001
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#define IDA_PCI_FIFO_NOT_FULL_MASK 0x00000002
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#define IDA_PCI_COMPLETION_STATUS_ACTIVE 0x00000001
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#define IDA_PCI_ISSUE_STATUS_CLEAR 0x00000002
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#define IDA_PCI_PHYS_ADDR_MASK 0xfffffffc
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#define IDA_PCI_COMPLETION_STATUS_MASK 0x00000003
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#define IDA_PCI_COMPLETION_ERROR 0x00000001
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#define IDA_PCI_COMPAQ_ID 0x00000E11
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#define IDA_PCI_DAZZLER_DEVICE_ID 0x0000AE10
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#define IDA_EISA_ID_MASKID_LOW 0xff000000
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#define IDA_PCI_NUM_ACCESS_RANGES 3
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typedef struct _PCI_IDENTIFIER {
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USHORT usVendorID;
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USHORT usDeviceID;
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} PCI_IDENTIFIER, *PPCI_IDENTIFIER;
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typedef struct _IDA_CONTEXT {
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UCHAR bHBAModel;
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USHORT usEisaSlot;
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PCI_IDENTIFIER PciIdentifier;
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PCI_ADDRESS PciAddress;
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} IDA_CONTEXT, *PIDA_CONTEXT;
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//
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// System Doorbell Interrupt Register bit definitions
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//
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#define SYSTEM_DOORBELL_COMMAND_LIST_COMPLETE 0x01
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#define SYSTEM_DOORBELL_SUBMIT_CHANNEL_CLEAR 0x02
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//
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// Local Doorbell Interrupt Register bit definitions
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//
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#define LOCAL_DOORBELL_COMMAND_LIST_SUBMIT 0x01
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#define LOCAL_DOORBELL_COMPLETE_CHANNEL_CLEAR 0x02
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//
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// Doorbell register channel clear bit
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//
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#define IDA_CHANNEL_CLEAR 0x01
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//
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// Interrupt Control register bit definitions
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//
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#define IDA_INTERRUPT_PENDING 0x02
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//
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// System doorbell register interrupt mask
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//
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#define IDA_COMPLETION_INTERRUPT_ENABLE 0x01
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//
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// Controller Configuration Register bit definitions
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//
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#define STANDARD_INTERFACE_ENABLE 0x01
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#define STANDARD_INTERFACE_SECONDARY_IO_ADDRESS 0x02
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#define BUS_MASTER_DISABLE 0x04
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#define SOFTWARE_RESET 0x08
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#define BUS_MASTER_INTERRUPT_11_ENABLE 0x10
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#define BUS_MASTER_INTERRUPT_10_ENABLE 0x20
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#define BUS_MASTER_INTERRUPT_14_ENABLE 0x40
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#define BUS_MASTER_INTERRUPT_15_ENABLE 0x80
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//
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// Disk configuration information
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//
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typedef struct _DISK_CONFIGURATION {
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UCHAR NumberLogicalDrives;
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IDENTIFY_LOGICAL_DRIVE LogicalDriveInformation[2];
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} DISK_CONFIGURATION, *PDISK_CONFIGURATION;
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//
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// structure for the flush/disable cache command
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//
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typedef struct _FLUSH_DISABLE {
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USHORT disable_flag;
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UCHAR reserved[30];
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} FLUSH_DISABLE, *PFLUSH_DISABLE;
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