397 lines
12 KiB
C
397 lines
12 KiB
C
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/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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ultra124.h
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Abstract:
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This file contains the structures and definitions that define
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the ULTRASTOR 124 EISA SCSI host bus adapter.
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Author:
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Mike Glass (MGLASS)
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Edward Syu (ES)
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Revision History:
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--*/
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#include "scsi.h"
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#define U124DEBUG 0
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#ifdef U124DEBUG
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#define DEBUGSTOP() \
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_asm {int 3}
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#else
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#define DEBUGSTOP()
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#endif
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//
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// SCATTER/GATHER definitions
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//
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#define MAXIMUM_EISA_SLOTS 0xF
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#define EISA_ADDRESS_BASE 0x0C80
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#define MAXIMUM_SG_DESCRIPTORS 33
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#define MAXIMUM_TRANSFER_LENGTH 0xFFFFFFFF
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//Note: U124 SG struct diff. from U24F/U14F
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typedef struct _SGD {
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ULONG Length;
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ULONG Address;
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} SGD, *PSGD;
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typedef struct _SDL {
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SGD Descriptor[MAXIMUM_SG_DESCRIPTORS];
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} SDL, *PSDL;
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//
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// MailBox SCSI Command Packet
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//
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#pragma pack(1)
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//
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// CSIR command
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//
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typedef struct _CSIR {
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UCHAR CSIROpcode; // byte 0
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UCHAR CSIR1; // byte 1
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UCHAR CSIR2; // byte 2
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UCHAR CSIR3; // byte 3
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UCHAR CSIR4; // byte 4
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UCHAR CSIR5; // byte 5
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} CSIR, *PCSIR;
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//CSP format for logical-drive-specific or general command
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typedef struct _MSCP {
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UCHAR OperationCode; // byte 00 (Opcode / Error Code)
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UCHAR DriveControl; // Drive: bit 5-7
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// ScatterGather bit 4
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// Control bit 3-0
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UCHAR SgDescriptorCount; // byte 02
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UCHAR Reserved; // byte 03
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ULONG DataPointer; // byte 04-07
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ULONG DriveLBA; // byte 08-0B
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ULONG DataLength; // byte 0C-0F
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PSCSI_REQUEST_BLOCK SrbAddress; // byte 10
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SDL Sdl; // byte 14
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CSIR CSIRBuffer; // for CSIR command
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} MSCP, *PMSCP;
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#define EnableScatterGather 0x10
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#pragma pack()
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//
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// Operation codes
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//
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// MailBox commands
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// Logical Drive Commands
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#define MSCP_TEST_DRIVE_READY 0x00
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#define MSCP_REZERO_DRIVE 0x01
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#define MSCP_READ_SECTOR 0x02
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#define MSCP_WRITE_SECTOR 0x03
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#define MSCP_VERIFY_SECTOR 0x04
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#define MSCP_SEEK_DRIVE 0x05
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// Logical Drive Maintenance Commands
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#define MSCP_INIT_DRIVE 0x10
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#define MSCP_SCAN_DRIVE 0x11
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#define MSCP_REBUILD 0x12 //unused
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#define MSCP_INTEGRITY_CHECK 0x13
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#define MSCP_INTEGRITY_FIX 0x14
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#define MSCP_FORCE_REBUILD 0x15
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// CSIR commands
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#define CSIR_READ_CAPACITY 0x01
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#define CSIR_DEFINE_LOG_DRIVE 0x02
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#define CSIR_ASSIGN_PARTITION 0x03
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#define CSIR_ISOLATE_CHANNEL 0x04
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#define CSIR_UNISOLATE_CHANNEL 0x05
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#define CSIR_REPORT_STATUS 0x06
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#define CSIR_RET_PHY_CONNECT 0x07
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#define CSIR_CTRL_DIAG 0x08
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#define CSIR_INIT_MAILBOX 0x09
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#define CSIR_RET_CONFIG 0x0A
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#define CSIR_RET_LOG_DRV_DEFINE 0x0B
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#define CSIR_RET_PART_INFO 0x0C
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#define CSIR_RESERVED_1 0x0D
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#define CSIR_RESERVED_2 0x0E
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#define CSIR_RET_UNITS_DOWN 0x0F
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#define CSIR_CLEAR_UNIT_DOWN 0x10
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#define CSIR_PREPARE_SHIP 0x11
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#define CSIR_WIPE_CTRL_NVRAM 0x11
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//
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// Host Adapter Error Codes
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//
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#define MSCP_NO_ERROR 0x00
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#define MSCP_ERROR 0x80
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#define CSIR_ERROR 0x80
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#define MSCP_INVALID_COMMAND 0x81
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#define MSCP_INVALID_PARAMETER 0x82
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#define MSCP_INVALID_DATA_LIST 0x83
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#define MSCP_LOG_DRIVE_UNDEFINE 0x84
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#define MSCP_DRIVE_NOT_PRESENT 0x88
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#define MSCP_LOG_DRIVE_NOT_READY 0x89
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#define MSCP_DRIVE_FAULT 0x8A
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#define MSCP_INTEGRITY_CHECK_FAIL 0x8B
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#define MSCP_RECOVERY_FAIL 0x8C //double error
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#define MSCP_SCSI_UNKNOWN_ERROR 0x8D
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#define MSCP_ADAPTER_ERROR 0x90
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// SubCodes for adapter error loaded into byte 7 of MSCP
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#define HA_NO_ERROR 0x00
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#define HA_BMIC_ERROR 0x44
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#define HA_ABORT_ERROR 0x84
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#define HA_SELECTION_TIME_OUT 0x91
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#define HA_DATA_OVER_UNDER_RUN 0x92
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#define HA_BUS_FREE_ERROR 0x93
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#define HA_INVALID_PHASE 0x94
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#define HA_ILLEGAL_COMMAND 0x96
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#define HA_REQ_SENSE_ERROR 0x9B
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#define HA_COMPLETE_MSG_ERROR 0x9F
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#define HA_BUS_RESET_ERROR 0xA3
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#define HA_TIME_OUT_ERROR 0x58
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#define HA_GENERAL_ERROR 0x59
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#define MSCP_TARGET_ERROR 0xA0
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//Subcode for SCSI target error
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// byte 7 of MSCP : SCSI sense key
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// byte 6/5 of MSCP : SCSI sense code
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#define MSCP_POWER_ON_DIAG_ERROR 0xB0
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//Subcode for diag. error (byte 4 of MSCP)
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#define DIAG_EPROM_CHKSUM_ERROR 0x01
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#define DIAG_CODE_RAM_ERROR 0x02
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#define DIAG_NVRAM_ERROR 0x03
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#define DIAG_BUFFER_RAM_ERROR 0x04
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#define DIAG_SCRIPT_RAM_ERROR 0x05
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#define DIAG_ISA_RAM_ERROR 0x06
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#define DIAG_BMIC_INIT_ERROR 0x07
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#define DIAG_PARITY_INIT_ERROR 0x08
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#define DIAG_CHANNEL_0_INIT_ERROR 0x09
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#define DIAG_CHANNEL_1_INIT_ERROR 0x0A
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#define DIAG_CHANNEL_2_INIT_ERROR 0x0B
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#define DIAG_CHANNEL_3_INIT_ERROR 0x0C
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#define DIAG_CHANNEL_4_INIT_ERROR 0x0D
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#define DIAG_ISA_INIT_ERROR 0x0E
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//
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// EISA Registers definition
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//
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#pragma pack(1)
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typedef struct _EISA_CONTROLLER {
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ULONG BoardId; // zC80
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UCHAR ExpansionBoard; // zC84
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UCHAR InterruptLevel; // zC85
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UCHAR AuxControl; // zC86
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UCHAR HostAdapterId; // zC87
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UCHAR RegisterRev1[40]; // zC88-zCAF
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UCHAR LocalDoorBellMask; // zCB0
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UCHAR LocalDoorBellInterrupt; // zCB1
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UCHAR SystemDoorBellMask; // zCB2
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UCHAR SystemDoorBellInterrupt; // zCB3
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UCHAR ErrorRegister; // zCB4
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UCHAR RegisterRev2[3]; // zCB5-zCB7
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UCHAR CSPByte0; // zCB8
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UCHAR CSPByte1; // zCB9
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UCHAR CSPByte2; // zCBA
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UCHAR CSPByte3; // zCBB
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UCHAR CSPByte4; // zCBC
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UCHAR CSPByte5; // zCBD
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UCHAR RegisterRev3[2]; // zCBE-zCBF
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ULONG OutGoingMailPointer; // zCC0
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ULONG InComingMailPointer; // zCC4
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} EISA_CONTROLLER, *PEISA_CONTROLLER;
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#pragma pack()
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//
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// UltraStor 124 board id
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//
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#define ULTRASTOR_124_EISA_ID 0x40126356
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//
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// Interrupt levels
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//
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#define US_INTERRUPT_LEVEL_15 0x10
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#define US_INTERRUPT_LEVEL_14 0x20
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#define US_INTERRUPT_LEVEL_11 0x40
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#define US_INTERRUPT_LEVEL_10 0x80
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//
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// Alternate address selection
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//
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#define US_SECONDARY_ADDRESS 0x08
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//
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// ISA TSR Port enabled
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//
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#define US_ISA_TSR_PORT_ENABLED 0x04
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//
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// Local interrupt status
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// System interrupt mask
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// 0xCB1
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// 0xCB2
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#define US_CSIR_IN_USE 0x10
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#define US_MSCP_IN_USE 0x01
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#define US_HBA_RESET 0x40
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#define US_ENABLE_SYSTEM_INTERRUPT 0x80
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#define US_ENABLE_CSIR_INTERRUPT 0x10
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#define US_ENABLE_MSCP_INTERRUPT 0x01
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//
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// System interrupt status
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// 0xCB3
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#define US_RESET_MSCP_COMPLETE 0x01
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#define US_MSCP_COMPLETE 0x01
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#define US_RESET_CSIR_COMPLETE 0x10
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#define US_CSIR_COMPLETE 0x10
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//
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// Error Register
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// 0xCB4
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#define DRIVE_DOWN 0x01
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#define CDB_6_BYTE 6 // Length of 6 byte CDB
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#define CDB_10_BYTE 10 // Length of 10 byte CDB
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#define CDB_12_BYTE 12 // Length of 12 byte CDB
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#define C6_OPCODE 0
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#define C6_LUN 1
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#define C6_LBA_2 2
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#define C6_LBA_1 3
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#define C6_XFRLEN 4
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#define C6_CONTROL 5
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#define C10_OPCODE 0
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#define C10_LUN 1
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#define C10_LBA_4 2
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#define C10_LBA_3 3
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#define C10_LBA_2 4
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#define C10_LBA_1 5
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#define C10_RESERVED 6
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#define C10_XFR_2 7
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#define C10_XFR_1 8
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#define C10_CONTROL 9
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#define C12_OPCODE 0
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#define C12_LUN 1
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#define C12_LBA_4 2
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#define C12_LBA_3 3
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#define C12_LBA_2 4
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#define C12_LBA_1 5
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#define C12_XFR_4 6
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#define C12_XFR_3 7
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#define C12_XFR_2 8
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#define C12_XFR_1 9
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#define C12_RESERVED 10
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#define C12_CONTROL 11
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// Read Capacity Data
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typedef struct _SCSIReadCapacity {
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UCHAR BlockCount[4]; //# of Logical Block Address
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UCHAR BlockLength[4]; //block length (in bytes)
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} SCSI_READCAPACITY, *PSCSI_READCAPACITY, *NPSCSI_READCAPCITY;
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//
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// The following definitions are used to convert SCSI & INTEL format
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//
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typedef struct _INTEL_4_BYTE {
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UCHAR Byte0;
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UCHAR Byte1;
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UCHAR Byte2;
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UCHAR Byte3;
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} INTEL_4_BYTE, *PINTEL_4_BYTE;
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typedef struct _INTEL_2_BYTE {
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UCHAR Byte0;
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UCHAR Byte1;
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} INTEL_2_BYTE, *PINTEL_2_BYTE;
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typedef struct _SCSI_2_BYTE {
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UCHAR S1;
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UCHAR S0;
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} SCSI_2_BYTE, *PSCSI_2_BYTE;
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typedef struct _SCSI_4_BYTE {
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UCHAR S3;
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UCHAR S2;
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UCHAR S1;
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UCHAR S0;
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} SCSI_4_BYTE, *PSCSI_4_BYTE;
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#define INTEL2_TO_SCSI2(ScsiTwo, IntelTwo) { \
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(ScsiTwo)->S0 = (Inteltwo)->Byte0; \
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(ScsiTwo)->S1 = (Inteltwo)->Byte1; \
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}
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#define SCSI2_TO_INTEL2(IntelTwo, ScsiTwo) { \
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(IntelTwo)->Byte0 = (ScsiTwo)->S0; \
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(IntelTwo)->Byte1 = (ScsiTwo)->S1; \
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}
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#define INTEL4_TO_SCSI2(Two, Four) { \
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ASSERT(!((Four)->Byte3)); \
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ASSERT(!((Four)->Byte2)); \
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(Two)->S0 = (Four)->Byte0; \
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(Two)->S1 = (Four)->Byte1; \
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}
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#define SCSI2_TO_INTEL4(Four, Two) { \
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(Four)->Byte0 = (Two)->S0; \
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(Four)->Byte1 = (Two)->S1; \
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(Four)->Byte2 = 0; \
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(Four)->Byte3 = 0; \
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}
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#define SCSI4_TO_INTEL4(IntelFour, ScsiFour) { \
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(IntelFour)->Byte0 = (ScsiFour)->S0; \
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(IntelFour)->Byte1 = (ScsiFour)->S1; \
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(IntelFour)->Byte2 = (ScsiFour)->S2; \
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(IntelFour)->Byte3 = (ScsiFour)->S3; \
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}
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#define INTEL4_TO_SCSI4(ScsiFour, IntelFour) { \
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(ScsiFour)->S0 = (IntelFour)->Byte0; \
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(ScsiFour)->S1 = (IntelFour)->Byte1; \
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(ScsiFour)->S2 = (IntelFour)->Byte2; \
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(ScsiFour)->S3 = (IntelFour)->Byte3; \
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}
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