702 lines
24 KiB
ArmAsm
702 lines
24 KiB
ArmAsm
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/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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apecsio.s
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Abstract:
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This contains assembler code routines for the Alpha AXP Eval Board eb64+.
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The module contains the functions to turn quasi virtual
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addresses into an Alpha superpage virtual address
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and then read or write based on the request.
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(We are using EV4 64-bit superpage mode.)
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Author:
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Joe Notarangelo 25-Oct-1993
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Environment:
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Executes in kernel mode.
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Revision History:
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Sameer Dekate 28-July-1994
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Made a common file alphaio.s for machine independent routines.
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--*/
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#include "apecs.h"
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#include "halalpha.h"
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SBTTL( "Write Control Register" )
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//++
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//
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// VOID
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// WRITE_EPIC_REGISTER(
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// IN PVOID RegisterQva,
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// IN ULONG Value
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// )
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//
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// Routine Description:
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//
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// Write a control register in the APECS memory or PCI controller
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// (COMANCHE and EPIC respectively).
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//
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// Arguments:
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//
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// RegisterQva(a0) - QVA of control register to be written.
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//
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// Value(a1) - Longword value to be written to the control register.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(WRITE_EPIC_REGISTER)
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ALTERNATE_ENTRY(WRITE_COMANCHE_REGISTER)
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, 5, t0 //
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ldiq t4, -0x4000 //
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sll t4, 28, t4 //
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or t0, t4, t0 // superpage mode
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.set volatile
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stl a1, (t0) // write the longword
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ldl t4, (t0) // read the the longword, to force
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// consistency (EPIC chip bug).
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mb // order the write
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.set novolatile
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ret zero, (ra) // return
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2: // flag bad QVAs
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BREAK_DEBUG_STOP // take a breakpoint
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ret zero, (ra) // return
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.end WRITE_EPIC_REGISTER
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SBTTL( "Read Control Register" )
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//++
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//
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// ULONG
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// READ_EPIC_REGISTER(
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// IN PVOID RegisterQva
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// )
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//
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// Routine Description:
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//
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// Read a control register in the APECS memory or PCI controller
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// (COMANCHE and EPIC respectively).
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//
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// Arguments:
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//
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// RegisterQva(a0) - QVA of control register to be written.
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//
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// Return Value:
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//
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// v0 - Return the value read from the control register.
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//
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//--
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LEAF_ENTRY(READ_EPIC_REGISTER)
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ALTERNATE_ENTRY(READ_COMANCHE_REGISTER)
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, 5, t0 //
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ldiq t4, -0x4000 //
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sll t4, 28, t4 //
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or t0, t4, t0 // superpage mode
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ldl v0, (t0) // read the register
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ret zero, (ra) // return
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2: // flag bad QVAs
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BREAK_DEBUG_STOP // take a breakpoint
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ret zero, (ra) // return
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.end READ_EPIC_REGISTER
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//
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// Values and structures used to access configuration space.
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//
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//
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// Define the QVA for the Configuration Cycle Type register within the
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// IOC. Physical Address = 1 A000 01C0
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//
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#define EPIC_HAXR2_QVA (0xad00000e)
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//
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// Define the configuration routines stack frame.
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//
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.struct 0
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CfgRa: .space 8 // return address
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CfgA0: .space 8 // saved ConfigurationAddress
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CfgA1: .space 8 // saved ConfigurationData/CycleType
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CfgA2: .space 8 // saved ConfigurationCycleType
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CfgFrameLength:
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//++
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//
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// ULONG
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// READ_CONFIG_UCHAR(
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// ULONG ConfigurationAddress,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read an unsigned byte from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA of configuration to be read.
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//
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// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// (v0) Returns the value of configuration space at the specified location.
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//
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// N.B. - This routine follows a protocol for reading from PCI configuration
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// space that allows the HAL or firmware to fixup and continue
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// execution if no device exists at the configuration target address.
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// The protocol requires 2 rules:
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// (1) The configuration space load must use a destination register
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// of v0
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// (2) The instruction immediately following the configuration space
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// load must use v0 as an operand (it must consume the value
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// returned by the load)
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//
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//--
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NESTED_ENTRY( READ_CONFIG_UCHAR, CfgFrameLength, zero )
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lda sp, -CfgFrameLength(sp) // allocate stack frame
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stq ra, CfgRa(sp) // save return address
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PROLOGUE_END // end prologue
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//
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// Merge the configuration cycle type into the HAXR2 register within
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// the EPIC.
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//
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stq a0, CfgA0(sp) // save configuration space address
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stq a1, CfgA1(sp) // save configuration cycle type
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ldil a0, EPIC_HAXR2_QVA // address of HAXR2
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bsr ra, READ_EPIC_REGISTER // read current value
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ldq a1, CfgA1(sp) // restore configuration cycle type
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bic v0, 0x3, t0 // clear config cycle type field
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bis a1, t0, a1 // merge config cycle type
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ldil a0, EPIC_HAXR2_QVA // address of HAXR2
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bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
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//
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// Perform the read from configuration space after restoring the
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// configuration space address.
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//
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ldq a0, CfgA0(sp) // restore configuration space address
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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and a0, 0x3, t3 // capture byte lane
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, IO_BIT_SHIFT, t0 //
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ldiq t4, -0x4000 //
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sll t4, 28, t4 //
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bis t0, t4, t0 // superpage mode
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bis t0, IO_BYTE_LEN, t0 // or in the byte enables
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ldl v0, (t0) // read the longword
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extbl v0, t3, v0 // return byte from requested lane
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// also, consume loaded value to cause
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// a pipeline stall
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2: //
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ldq ra, CfgRa(sp) // restore return address
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lda sp, CfgFrameLength(sp) // deallocate stack frame
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ret zero, (ra) // return
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.end READ_CONFIG_UCHAR
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//++
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//
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// VOID
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// WRITE_CONFIG_UCHAR(
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// ULONG ConfigurationAddress,
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// UCHAR ConfigurationData,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read an unsigned byte from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA to write.
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//
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// ConfigurationData(a1) - Supplies the data to be written.
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//
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// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// None.
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//
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// N.B. - The configuration address must exist within the address space
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// allocated to an existing PCI device. Otherwise, the access
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// below will initiate an unrecoverable machine check.
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//
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//--
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NESTED_ENTRY( WRITE_CONFIG_UCHAR, CfgFrameLength, zero )
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lda sp, -CfgFrameLength(sp) // allocate stack frame
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stq ra, CfgRa(sp) // save return address
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PROLOGUE_END // end prologue
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//
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// Merge the configuration cycle type into the HAXR2 register within
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// the EPIC.
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//
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stq a0, CfgA0(sp) // save configuration space address
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stq a1, CfgA1(sp) // save configuration data
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stq a2, CfgA2(sp) // save configuration cycle type
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ldil a0, EPIC_HAXR2_QVA // address of HAXR2
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bsr ra, READ_EPIC_REGISTER // read current value
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ldq a1, CfgA2(sp) // restore configuration cycle type
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bic v0, 0x3, t0 // clear config cycle type field
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bis a1, t0, a1 // merge config cycle type
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ldil a0, EPIC_HAXR2_QVA // address of HAXR2
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bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
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//
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// Perform the read from configuration space after restoring the
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// configuration space address and data.
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//
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ldq a0, CfgA0(sp) // restore configuration space address
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ldq a1, CfgA1(sp) // restore configuration data
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and a0, QVA_SELECTORS, t1 // get qva selector bits
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and a0, 0x3, t3 // capture byte lane
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xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
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bne t1, 2f // if ne, iff failed
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zap a0, 0xf0, a0 // clear <63:32>
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bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
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sll a0, IO_BIT_SHIFT, t0 //
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ldiq t4, -0x4000 //
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sll t4, 28, t4 //
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bis t0, t4, t0 // superpage mode
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bis t0, IO_BYTE_LEN, t0 // or in the byte length indicator
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insbl a1, t3, t4 // put byte in the appropriate lane
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stl t4, (t0) // write the configuration byte
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mb // synchronize
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2: //
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ldq ra, CfgRa(sp) // restore return address
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lda sp, CfgFrameLength(sp) // deallocate stack frame
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ret zero, (ra) // return
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.end WRITE_CONFIG_UCHAR
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//++
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//
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// ULONG
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// READ_CONFIG_USHORT(
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// ULONG ConfigurationAddress,
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// ULONG ConfigurationCycleType
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// )
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//
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// Routine Description:
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//
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// Read a longword from PCI configuration space.
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//
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// Arguments:
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//
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// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
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//
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// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
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//
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// Return Value:
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//
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// (v0) Returns the value of configuration space at the specified location.
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//
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// N.B. - This routine follows a protocol for reading from PCI configuration
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// space that allows the HAL or firmware to fixup and continue
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// execution if no device exists at the configuration target address.
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// The protocol requires 2 rules:
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// (1) The configuration space load must use a destination register
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// of v0
|
|||
|
|
// (2) The instruction immediately following the configuration space
|
|||
|
|
// load must use v0 as an operand (it must consume the value
|
|||
|
|
// returned by the load)
|
|||
|
|
//--
|
|||
|
|
|
|||
|
|
NESTED_ENTRY( READ_CONFIG_USHORT, CfgFrameLength, zero )
|
|||
|
|
|
|||
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|||
|
|
stq ra, CfgRa(sp) // save return address
|
|||
|
|
|
|||
|
|
PROLOGUE_END // end prologue
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Merge the configuration cycle type into the HAXR2 register within
|
|||
|
|
// the EPIC.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
stq a0, CfgA0(sp) // save configuration space address
|
|||
|
|
stq a1, CfgA1(sp) // save configuration cycle type
|
|||
|
|
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, READ_EPIC_REGISTER // read current value
|
|||
|
|
|
|||
|
|
ldq a1, CfgA1(sp) // restore configuration cycle type
|
|||
|
|
bic v0, 0x3, t0 // clear config cycle type field
|
|||
|
|
bis a1, t0, a1 // merge config cycle type
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Perform the read from configuration space after restoring the
|
|||
|
|
// configuration space address.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
ldq a0, CfgA0(sp) // restore configuration space address
|
|||
|
|
|
|||
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|||
|
|
and a0, 0x3, t3 // capture word offset
|
|||
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
|
|||
|
|
bne t1, 2f // if ne, iff failed
|
|||
|
|
|
|||
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|||
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
|
|||
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|||
|
|
ldiq t4, -0x4000 //
|
|||
|
|
sll t4, 28, t4 //
|
|||
|
|
bis t0, t4, t0 // superpage mode
|
|||
|
|
|
|||
|
|
bis t0, IO_WORD_LEN, t0 // or in the byte enables
|
|||
|
|
|
|||
|
|
ldl v0, (t0) // read the longword
|
|||
|
|
extwl v0, t3, v0 // return word from requested lanes
|
|||
|
|
// also, consume loaded value to cause
|
|||
|
|
// a pipeline stall
|
|||
|
|
2: //
|
|||
|
|
ldq ra, CfgRa(sp) // restore return address
|
|||
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|||
|
|
ret zero, (ra) // return
|
|||
|
|
|
|||
|
|
.end READ_CONFIG_USHORT
|
|||
|
|
|
|||
|
|
//++
|
|||
|
|
//
|
|||
|
|
// VOID
|
|||
|
|
// WRITE_CONFIG_USHORT(
|
|||
|
|
// ULONG ConfigurationAddress,
|
|||
|
|
// USHORT ConfigurationData,
|
|||
|
|
// ULONG ConfigurationCycleType
|
|||
|
|
// )
|
|||
|
|
//
|
|||
|
|
// Routine Description:
|
|||
|
|
//
|
|||
|
|
// Read a longword from PCI configuration space.
|
|||
|
|
//
|
|||
|
|
// Arguments:
|
|||
|
|
//
|
|||
|
|
// ConfigurationAddress(a0) - Supplies the QVA to write.
|
|||
|
|
//
|
|||
|
|
// ConfigurationData(a1) - Supplies the data to be written.
|
|||
|
|
//
|
|||
|
|
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
|
|||
|
|
//
|
|||
|
|
// Return Value:
|
|||
|
|
//
|
|||
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|||
|
|
//
|
|||
|
|
// N.B. - The configuration address must exist within the address space
|
|||
|
|
// allocated to an existing PCI device. Otherwise, the access
|
|||
|
|
// below will initiate an unrecoverable machine check.
|
|||
|
|
//
|
|||
|
|
//--
|
|||
|
|
|
|||
|
|
NESTED_ENTRY( WRITE_CONFIG_USHORT, CfgFrameLength, zero )
|
|||
|
|
|
|||
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|||
|
|
stq ra, CfgRa(sp) // save return address
|
|||
|
|
|
|||
|
|
PROLOGUE_END // end prologue
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Merge the configuration cycle type into the HAXR2 register within
|
|||
|
|
// the EPIC.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
stq a0, CfgA0(sp) // save configuration space address
|
|||
|
|
stq a1, CfgA1(sp) // save configuration data
|
|||
|
|
stq a2, CfgA2(sp) // save configuration cycle type
|
|||
|
|
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, READ_EPIC_REGISTER // read current value
|
|||
|
|
|
|||
|
|
ldq a1, CfgA2(sp) // restore configuration cycle type
|
|||
|
|
bic v0, 0x3, t0 // clear config cycle type field
|
|||
|
|
bis a1, t0, a1 // merge config cycle type
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Perform the read from configuration space after restoring the
|
|||
|
|
// configuration space address and data.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
ldq a0, CfgA0(sp) // restore configuration space address
|
|||
|
|
ldq a1, CfgA1(sp) // restore configuration data
|
|||
|
|
|
|||
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|||
|
|
and a0, 0x3, t3 // capture word offset
|
|||
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
|
|||
|
|
bne t1, 2f // if ne, iff failed
|
|||
|
|
|
|||
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|||
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
|
|||
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|||
|
|
ldiq t4, -0x4000 //
|
|||
|
|
sll t4, 28, t4 //
|
|||
|
|
bis t0, t4, t0 // superpage mode
|
|||
|
|
|
|||
|
|
bis t0, IO_WORD_LEN, t0 // or in the byte enables
|
|||
|
|
|
|||
|
|
inswl a1, t3, t4 // put data to appropriate lane
|
|||
|
|
stl t4, (t0) // read the longword
|
|||
|
|
mb // synchronize
|
|||
|
|
2: //
|
|||
|
|
ldq ra, CfgRa(sp) // restore return address
|
|||
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|||
|
|
ret zero, (ra) // return
|
|||
|
|
|
|||
|
|
.end WRITE_CONFIG_USHORT
|
|||
|
|
|
|||
|
|
//++
|
|||
|
|
//
|
|||
|
|
// ULONG
|
|||
|
|
// READ_CONFIG_ULONG(
|
|||
|
|
// ULONG ConfigurationAddress,
|
|||
|
|
// ULONG ConfigurationCycleType
|
|||
|
|
// )
|
|||
|
|
//
|
|||
|
|
// Routine Description:
|
|||
|
|
//
|
|||
|
|
// Read a longword from PCI configuration space.
|
|||
|
|
//
|
|||
|
|
// Arguments:
|
|||
|
|
//
|
|||
|
|
// ConfigurationAddress(a0) - Supplies the QVA of quadword to be read.
|
|||
|
|
//
|
|||
|
|
// ConfigurationCycleType(a1) - Supplies the type of the configuration cycle.
|
|||
|
|
//
|
|||
|
|
// Return Value:
|
|||
|
|
//
|
|||
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|||
|
|
//
|
|||
|
|
// N.B. - This routine follows a protocol for reading from PCI configuration
|
|||
|
|
// space that allows the HAL or firmware to fixup and continue
|
|||
|
|
// execution if no device exists at the configuration target address.
|
|||
|
|
// The protocol requires 2 rules:
|
|||
|
|
// (1) The configuration space load must use a destination register
|
|||
|
|
// of v0
|
|||
|
|
// (2) The instruction immediately following the configuration space
|
|||
|
|
// load must use v0 as an operand (it must consume the value
|
|||
|
|
// returned by the load)
|
|||
|
|
//--
|
|||
|
|
|
|||
|
|
NESTED_ENTRY( READ_CONFIG_ULONG, CfgFrameLength, zero )
|
|||
|
|
|
|||
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|||
|
|
stq ra, CfgRa(sp) // save return address
|
|||
|
|
|
|||
|
|
PROLOGUE_END // end prologue
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Merge the configuration cycle type into the HAXR2 register within
|
|||
|
|
// the EPIC.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
stq a0, CfgA0(sp) // save configuration space address
|
|||
|
|
stq a1, CfgA1(sp) // save configuration cycle type
|
|||
|
|
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, READ_EPIC_REGISTER // read current value
|
|||
|
|
|
|||
|
|
ldq a1, CfgA1(sp) // restore configuration cycle type
|
|||
|
|
bic v0, 0x3, t0 // clear config cycle type field
|
|||
|
|
bis a1, t0, a1 // merge config cycle type
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Perform the read from configuration space after restoring the
|
|||
|
|
// configuration space address.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
ldq a0, CfgA0(sp) // restore configuration space address
|
|||
|
|
|
|||
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|||
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
|
|||
|
|
bne t1, 2f // if ne, iff failed
|
|||
|
|
|
|||
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|||
|
|
bic a0, QVA_ENABLE,a0 // clear QVA fields so shift is correct
|
|||
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|||
|
|
ldiq t4, -0x4000 //
|
|||
|
|
sll t4, 28, t4 //
|
|||
|
|
or t0, t4, t0 // superpage mode
|
|||
|
|
|
|||
|
|
or t0, IO_LONG_LEN, t0 // or in the byte enables
|
|||
|
|
|
|||
|
|
ldl v0, (t0) // read the longword
|
|||
|
|
bis v0, zero, t1 // consume loaded value to cause
|
|||
|
|
// a pipeline stall
|
|||
|
|
2: //
|
|||
|
|
ldq ra, CfgRa(sp) // restore return address
|
|||
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|||
|
|
ret zero, (ra) // return
|
|||
|
|
|
|||
|
|
.end READ_CONFIG_ULONG
|
|||
|
|
|
|||
|
|
|
|||
|
|
//++
|
|||
|
|
//
|
|||
|
|
// VOID
|
|||
|
|
// WRITE_CONFIG_ULONG(
|
|||
|
|
// ULONG ConfigurationAddress,
|
|||
|
|
// ULONG ConfigurationData,
|
|||
|
|
// ULONG ConfigurationCycleType
|
|||
|
|
// )
|
|||
|
|
//
|
|||
|
|
// Routine Description:
|
|||
|
|
//
|
|||
|
|
// Read a longword from PCI configuration space.
|
|||
|
|
//
|
|||
|
|
// Arguments:
|
|||
|
|
//
|
|||
|
|
// ConfigurationAddress(a0) - Supplies the QVA to write.
|
|||
|
|
//
|
|||
|
|
// ConfigurationData(a1) - Supplies the data to be written.
|
|||
|
|
//
|
|||
|
|
// ConfigurationCycleType(a2) - Supplies the type of the configuration cycle.
|
|||
|
|
//
|
|||
|
|
// Return Value:
|
|||
|
|
//
|
|||
|
|
// (v0) Returns the value of configuration space at the specified location.
|
|||
|
|
//
|
|||
|
|
// N.B. - The configuration address must exist within the address space
|
|||
|
|
// allocated to an existing PCI device. Otherwise, the access
|
|||
|
|
// below will initiate an unrecoverable machine check.
|
|||
|
|
//
|
|||
|
|
//--
|
|||
|
|
|
|||
|
|
NESTED_ENTRY( WRITE_CONFIG_ULONG, CfgFrameLength, zero )
|
|||
|
|
|
|||
|
|
lda sp, -CfgFrameLength(sp) // allocate stack frame
|
|||
|
|
stq ra, CfgRa(sp) // save return address
|
|||
|
|
|
|||
|
|
PROLOGUE_END // end prologue
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Merge the configuration cycle type into the HAXR2 register within
|
|||
|
|
// the EPIC.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
stq a0, CfgA0(sp) // save configuration space address
|
|||
|
|
stq a1, CfgA1(sp) // save configuration data
|
|||
|
|
stq a2, CfgA2(sp) // save configuration cycle type
|
|||
|
|
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, READ_EPIC_REGISTER // read current value
|
|||
|
|
|
|||
|
|
ldq a1, CfgA2(sp) // restore configuration cycle type
|
|||
|
|
bic v0, 0x3, t0 // clear config cycle type field
|
|||
|
|
bis a1, t0, a1 // merge config cycle type
|
|||
|
|
ldil a0, EPIC_HAXR2_QVA // address of HAXR2
|
|||
|
|
bsr ra, WRITE_EPIC_REGISTER // write updated HAXR2
|
|||
|
|
|
|||
|
|
//
|
|||
|
|
// Perform the read from configuration space after restoring the
|
|||
|
|
// configuration space address and data.
|
|||
|
|
//
|
|||
|
|
|
|||
|
|
ldq a0, CfgA0(sp) // restore configuration space address
|
|||
|
|
ldq a1, CfgA1(sp) // restore configuration data
|
|||
|
|
|
|||
|
|
and a0, QVA_SELECTORS, t1 // get qva selector bits
|
|||
|
|
xor t1, QVA_ENABLE, t1 // ok iff QVA_ENABLE set in selectors
|
|||
|
|
bne t1, 2f // if ne, iff failed
|
|||
|
|
|
|||
|
|
zap a0, 0xf0, a0 // clear <63:32>
|
|||
|
|
bic a0, QVA_ENABLE, a0 // clear QVA fields so shift is correct
|
|||
|
|
sll a0, IO_BIT_SHIFT, t0 //
|
|||
|
|
ldiq t4, -0x4000 //
|
|||
|
|
sll t4, 28, t4 //
|
|||
|
|
bis t0, t4, t0 // superpage mode
|
|||
|
|
|
|||
|
|
bis t0, IO_LONG_LEN, t0 // or in the byte enables
|
|||
|
|
|
|||
|
|
stl a1, (t0) // write the longword
|
|||
|
|
mb // synchronize
|
|||
|
|
2: //
|
|||
|
|
ldq ra, CfgRa(sp) // restore return address
|
|||
|
|
lda sp, CfgFrameLength(sp) // deallocate stack frame
|
|||
|
|
ret zero, (ra) // return
|
|||
|
|
|
|||
|
|
.end WRITE_CONFIG_ULONG
|