188 lines
4.5 KiB
C
188 lines
4.5 KiB
C
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/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Copyright (c) 1991 Microsoft Corporation
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Copyright (c) 1992, 1993 Digital Equipment Corporation
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Module Name:
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halpcsl.h
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Abstract:
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This header file includes the definitions for standard PC serial
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port UARTs.
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Stolen from jazzserp.h, which is a slightly different chip-
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it has a 16 byte fifo - we are just double buffered.
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Author:
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David N. Cutler (davec) 28-Apr-1991
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Miche Baker-Harvey (miche) 01-June-1992
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Revision History:
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--*/
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#ifndef _HALPCSL_
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#define _HALPCSL_
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//
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// Define base port numbers for serial lines inside the combo chip
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//
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#define COMA_PORT_BASE 0x3f8
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#define COMB_PORT_BASE 0x2f8
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//
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// Define serial port read registers structure.
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//
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typedef struct _SP_READ_REGISTERS {
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UCHAR ReceiveBuffer;
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UCHAR InterruptEnable;
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UCHAR InterruptId;
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UCHAR LineControl;
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UCHAR ModemControl;
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UCHAR LineStatus;
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UCHAR ModemStatus;
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UCHAR ScratchPad;
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} SP_READ_REGISTERS, *PSP_READ_REGISTERS;
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//
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// Define define serial port write registers structure.
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//
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typedef struct _SP_WRITE_REGISTERS {
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UCHAR TransmitBuffer;
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UCHAR InterruptEnable;
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UCHAR FifoControl;
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UCHAR LineControl;
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UCHAR ModemControl;
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UCHAR Reserved1;
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UCHAR ModemStatus;
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UCHAR ScratchPad;
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} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS;
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//
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// Define serial port interrupt enable register structure.
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//
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typedef struct _SP_INTERRUPT_ENABLE {
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UCHAR ReceiveEnable : 1;
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UCHAR TransmitEnable : 1;
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UCHAR LineStatusEnable : 1;
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UCHAR ModemStatusEnable : 1;
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UCHAR Reserved1 : 4;
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} SP_INTERRUPT_ENABLE, *PSP_INTERRUPT_ENABLE;
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//
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// Define serial port interrupt id register structure.
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//
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typedef struct _SP_INTERRUPT_ID {
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UCHAR InterruptPending : 1;
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UCHAR Identification : 3;
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UCHAR Reserved1 : 2;
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UCHAR FifoEnabled : 2; // always read as 0
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} SP_INTERRUPT_ID, *PSP_INTERRUPT_ID;
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//
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// Define serial port fifo control register structure.
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// This register is here for software compatibility, but there is
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// no FIFO on the 16C452
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//
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typedef struct _SP_FIFO_CONTROL {
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UCHAR FifoEnable : 1;
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UCHAR ReceiveFifoReset : 1;
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UCHAR TransmitFifoReset : 1;
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UCHAR DmaModeSelect : 1;
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UCHAR Reserved1 : 2;
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UCHAR ReceiveFifoLevel : 2;
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} SP_FIFO_CONTROL, *PSP_FIFO_CONTROL;
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//
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// Define serial port line control register structure.
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//
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typedef struct _SP_LINE_CONTROL {
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UCHAR CharacterSize : 2;
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UCHAR StopBits : 1;
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UCHAR ParityEnable : 1;
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UCHAR EvenParity : 1;
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UCHAR StickParity : 1;
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UCHAR SetBreak : 1;
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UCHAR DivisorLatch : 1;
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} SP_LINE_CONTROL, *PSP_LINE_CONTROL;
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//
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// Line status register character size definitions.
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//
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#define FIVE_BITS 0x0 // five bits per character
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#define SIX_BITS 0x1 // six bits per character
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#define SEVEN_BITS 0x2 // seven bits per character
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#define EIGHT_BITS 0x3 // eight bits per character
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//
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// Line speed divisor definition. We get our baud rate clock
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// from the 82C106.
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//
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#define BAUD_RATE_2400 48 // divisor for 2400 baud
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#define BAUD_RATE_4800 24 // divisor for 4800 baud
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#define BAUD_RATE_9600 12 // divisor for 9600 baud
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#define BAUD_RATE_19200 6 // divisor for 19200 baud
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#define BAUD_RATE_38400 3 // divisor for 38400 baud
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#define BAUD_RATE_57600 2 // divisor for 57600 baud
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#define BAUD_RATE_115200 1 // divisor for 115200 baud
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//
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// Define serial port modem control register structure.
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//
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typedef struct _SP_MODEM_CONTROL {
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UCHAR DataTerminalReady : 1;
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UCHAR RequestToSend : 1;
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UCHAR Reserved1 : 1;
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UCHAR Interrupt : 1;
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UCHAR loopBack : 1;
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UCHAR Reserved2 : 3;
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} SP_MODEM_CONTROL, *PSP_MODEM_CONTROL;
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//
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// Define serial port line status register structure.
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//
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typedef struct _SP_LINE_STATUS {
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UCHAR DataReady : 1;
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UCHAR OverrunError : 1;
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UCHAR ParityError : 1;
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UCHAR FramingError : 1;
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UCHAR BreakIndicator : 1;
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UCHAR TransmitHoldingEmpty : 1;
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UCHAR TransmitEmpty : 1;
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UCHAR ReceiveFifoError : 1;
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} SP_LINE_STATUS, *PSP_LINE_STATUS;
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//
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// Define serial port modem status register structure.
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//
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typedef struct _SP_MODEM_STATUS {
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UCHAR DeltaClearToSend : 1;
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UCHAR DeltaDataSetReady : 1;
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UCHAR TrailingRingIndicator : 1;
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UCHAR DeltaReceiveDetect : 1;
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UCHAR ClearToSend : 1;
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UCHAR DataSetReady : 1;
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UCHAR RingIndicator : 1;
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UCHAR ReceiveDetect : 1;
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} SP_MODEM_STATUS, *PSP_MODEM_STATUS;
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#endif // _HALPCSL_
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