292 lines
5.3 KiB
C
292 lines
5.3 KiB
C
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: pxhalp.h $
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* $Revision: 1.15 $
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* $Date: 1996/05/15 00:06:21 $
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* $Locker: $
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*/
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/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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pxhalp.h
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Abstract:
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This header file defines the private Hardware Architecture Layer (HAL)
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PowerPC specific interfaces, defines and structures.
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Author:
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Jeff Havens (jhavens) 20-Jun-91
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Revision History:
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Jim Wooldridge (jimw@austin.vnet.ibm.com) Initial PowerPC port
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Added externs for HalpInterruptBase,HalpPciConfigBase
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Added extern for HalpIoControlBase
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Added prototype for HalpHandleDecrementerInterrupt (was in halp.h)
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changed adapter object structure to be compatible with the intel HAL
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--*/
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#ifndef _PXHALP_
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#define _PXHALP_
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//
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// Define global data used to locate the IO control space, the interrupt
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// acknowlege, and the Pci config base.
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//
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extern PVOID HalpIoControlBase;
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extern PVOID HalpIoMemoryBase;
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extern PVOID HalpInterruptBase;
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extern PVOID HalpPciConfigBase;
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extern PVOID HalpErrorAddressRegister;
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extern PVOID HalpPciIsaBridgeConfigBase;
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//
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// prototype x86 emulator
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//
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extern BOOLEAN HalpInitX86Emulator(VOID);
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//
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// Define adapter object structure.
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//
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//
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// The MAXIMUM_MAP_BUFFER_SIZE defines the maximum map buffers which the system
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// will allocate for devices which require phyically contigous buffers.
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//
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#define MAXIMUM_MAP_BUFFER_SIZE 0x40000
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//
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// Define the initial buffer allocation size for a map buffers for systems with
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// no memory which has a physical address greater than MAXIMUM_PHYSICAL_ADDRESS.
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//
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#define INITIAL_MAP_BUFFER_SMALL_SIZE 0x10000
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//
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// Define the initial buffer allocation size for a map buffers for systems with
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// no memory which has a physical address greater than MAXIMUM_PHYSICAL_ADDRESS.
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//
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#define INITIAL_MAP_BUFFER_LARGE_SIZE 0x30000
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//
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// Define the incremental buffer allocation for a map buffers.
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//
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#define INCREMENT_MAP_BUFFER_SIZE 0x10000
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//
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// Define the maximum number of map registers that can be requested at one time
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// if actual map registers are required for the transfer.
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//
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#define MAXIMUM_ISA_MAP_REGISTER 16
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//
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// Define the maximum physical address which can be handled by an Isa card.
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//
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#define MAXIMUM_PHYSICAL_ADDRESS 0x01000000
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//
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// Define the scatter/gather flag for the Map Register Base.
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//
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#define NO_SCATTER_GATHER 0x00000001
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//
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// Define the copy buffer flag for the index.
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//
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#define COPY_BUFFER 0XFFFFFFFF
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//
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// Define adapter object structure.
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//
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typedef struct _ADAPTER_OBJECT {
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CSHORT Type;
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CSHORT Size;
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struct _ADAPTER_OBJECT *MasterAdapter;
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ULONG MapRegistersPerChannel;
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PVOID AdapterBaseVa;
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PVOID MapRegisterBase;
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ULONG NumberOfMapRegisters;
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ULONG CommittedMapRegisters;
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struct _WAIT_CONTEXT_BLOCK *CurrentWcb;
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KDEVICE_QUEUE ChannelWaitQueue;
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PKDEVICE_QUEUE RegisterWaitQueue;
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LIST_ENTRY AdapterQueue;
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KSPIN_LOCK SpinLock;
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PRTL_BITMAP MapRegisters;
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PUCHAR PagePort;
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UCHAR ChannelNumber;
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UCHAR AdapterNumber;
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USHORT DmaPortAddress;
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UCHAR AdapterMode;
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BOOLEAN NeedsMapRegisters;
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BOOLEAN MasterDevice;
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BOOLEAN Width16Bits;
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BOOLEAN ScatterGather;
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BOOLEAN IsaBusMaster;
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INTERFACE_TYPE InterfaceType; // spec what bus this adapter is on
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} ADAPTER_OBJECT;
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//
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// Define function prototypes.
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//
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PADAPTER_OBJECT
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HalpAllocateIsaAdapter(
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IN PDEVICE_DESCRIPTION DeviceDescription,
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OUT PULONG NumberOfMapRegisters
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);
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BOOLEAN
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HalpCreateSioStructures(
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VOID
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);
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VOID
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HalpDisableSioInterrupt(
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IN ULONG Vector
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);
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BOOLEAN
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HalpHandleExternalInterrupt(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PVOID TrapFrame
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);
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BOOLEAN
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HalpFieldExternalInterrupt(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PVOID TrapFrame
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);
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BOOLEAN
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HalpHandleDecrementerInterrupt (
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PVOID TrapFrame
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);
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VOID
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HalpIsaMapTransfer(
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IN PADAPTER_OBJECT AdapterObject,
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IN ULONG Offset,
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IN ULONG Length,
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IN BOOLEAN WriteToDevice
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);
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VOID
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HalpEnableSioInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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);
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BOOLEAN
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HalpAllocateMapBuffer(
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VOID
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);
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ULONG
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HalpUpdateDecrementer(
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ULONG
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);
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BOOLEAN
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HalpPhase0MapBusConfigSpace(
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VOID
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);
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VOID
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HalpPhase0UnMapBusConfigSpace(
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VOID
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);
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ULONG
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HalpPhase0GetPciDataByOffset(
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ULONG BusNumber,
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ULONG SlotNumber,
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PUCHAR Buffer,
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ULONG Offset,
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ULONG Length
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);
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ULONG
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HalpPhase0SetPciDataByOffset(
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ULONG BusNumber,
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ULONG SlotNumber,
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PUCHAR Buffer,
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ULONG Offset,
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ULONG Length
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);
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PVOID
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KePhase0MapIo(
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IN PVOID PhysicalMemoryBase,
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IN ULONG MemorySize
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);
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VOID
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KePhase0DeleteIoMap(
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IN PVOID PhysicalMemoryBase,
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IN ULONG MemorySize
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);
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ULONG
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HalpCalibrateTB(
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VOID
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);
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VOID
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HalpZeroPerformanceCounter(
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VOID
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);
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VOID
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HalpResetIrqlAfterInterrupt(
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KIRQL TargetIrql
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);
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VOID
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HalpLockDisplayString(
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PVOID
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);
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BOOLEAN
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HalpCacheSweepSetup(
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VOID
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);
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VOID
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HalpSweepPhysicalRangeInBothCaches(
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ULONG Page,
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ULONG Offset,
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ULONG Length
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);
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VOID
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HalpSweepPhysicalIcacheRange(
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ULONG Page,
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ULONG Offset,
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ULONG Length
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);
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#endif // _PXHALP_
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