434 lines
14 KiB
ArmAsm
434 lines
14 KiB
ArmAsm
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//++
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//
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// Copyright (C) 1993-1995 IBM Corporation
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//
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// Copyright (C) 1994-1995 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// pxreset.s
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//
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// Abstract:
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//
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// This module implements the routine HalpPowerPcReset, which can be
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// used to return the PowerPC to Big Endian with cache flushed and
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// branches to the rom based machine reset handler.
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//
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//
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// Environment:
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//
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// Kernel mode only.
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//
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//
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//--
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#include "kxppc.h"
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.set C_LINE_SZ, 64
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.set C_LINE_CNT, 64
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.set C_SETS, 8
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.set C_SIZE, C_LINE_SZ * C_LINE_CNT * C_SETS
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.set HID0, 1008
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.set DISABLES, MASK_SPR(MSR_DR,1) | MASK_SPR(MSR_IR,1)
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.set H0_603_DCE, 0x4000 // 603 Data Cache Enable
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.set H0_603_ICE, 0x8000 // 603 Instruction Cache Enable
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.set H0_603_ICFI, 0x0800 // 603 I-Cache Flash Invalidate
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.set H0_604_DCE, 0x4000 // 604 Data Cache Enable
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.set H0_604_ICE, 0x8000 // 604 Instruction Cache Enable
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.set H0_604_DCIA, 0x0400 // 604 I-Cache Invalidate All
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.set H0_604_ICIA, 0x0800 // 604 I-Cache Invalidate All
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.set TLB_CLASSES_601, 128 // 601 tlb has 128 congruence classes
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.set TLB_CLASSES_603, 32 // 603 tlb has 32 congruence classes
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.set TLB_CLASSES_604, 64 // 604 tlb has 64 congruence classes
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LEAF_ENTRY(HalpPowerPcReset)
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LWI(r.4, 0xfff00100) // address of rom reset handler
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mfspr r.5, HID0
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mfpvr r.31 // determine processor type
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li r.6, 0
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li r.7, 0x92
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oris r.7, r.7, 0x8000
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mfmsr r.8
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rlwinm r.8, r.8, 0, ~MASK_SPR(MSR_EE,1) // disable interrupts
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mtmsr r.8
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cror 0,0,0 // N.B. 603e/ev Errata 15
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//
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// invalidate all tlb entries
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//
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li r.3, TLB_CLASSES_601 // use largest known number of
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// congruence classes
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mtctr r.3 // number of classes = iteration count
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zaptlb: tlbie r.3 // invalidate tlb congruence class
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addi r.3, r.3, 4096 // increment to next class address
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bdnz zaptlb // loop through all classes
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srwi r.31, r.31, 16 // isolate processor type
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cmpwi r.31, 1 // is 601?
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bl here // get current address
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here:
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mflr r.9 // (r.9) = &here
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rlwinm r.9, r.9, 0, 0x7fffffff // convert address to physical
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bne not_601
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//
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// processor is a 601
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//
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rlwinm r.5, r.5, 0, ~(0x0008) // turn off little endian
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//
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// disable instruction and data relocation and switch
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// interrupt prefix to fetch from ROM
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//
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andi. r.8, r.8, ~DISABLES & 0xffff
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ori r.8, r.8, MASK_SPR(MSR_IP,1)
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mtsrr1 r.8 // this will also be target state
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nop // for rfi
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//
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// Ensure all code from 'cachem' to 'end_little' is in cache by loading a
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// byte in each address line in that range.
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addi r.9, r.9, cachem-here // (r.9) = physical &cachem
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// r.9 now contains the physical address of cachem. (assuming
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// this code was loaded as part of kernel which is loaded at
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// physical 0 = virtual 0x80000000). We effect the switch to
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// physical addressing thru an rfi with the target state set
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// to resume at cachem with relocation and interrupts disabled.
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mtsrr0 r.9 // address of cachem for rfi
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addi r.10, r.9, end_little-cachem // (r.10) = &end_little
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addi r.11, r.9, HalpPowerPcReset.end-cachem // (r.11) = &reset_end
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addi r.12, r.9, -C_LINE_SZ // bias addr for 1st iteration by
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// amount added by lbzu prior to load
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rfi // switch
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cachem:
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lbzu r.13, C_LINE_SZ(r.12) // get byte at (r.13)+C_LINE_SZ
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cmplw r.12, r.10 // bumping r.12 by C_LINE_SZ
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addi r.13, r.13, 1 // ensure load completed.
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blt cachem // get all in range here-end_little.
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mtsrr0 r.4 // set rom reset target for next rfi
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lis r.9, 0x87f0 // Segment register base 0x87f00000
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li r.10, 0xf // Set all 16 segment registers
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li r.11, 0
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mtibatl 0, r.6 // zero bat 0-3 upper and lower
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mtibatu 0, r.6
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mtibatl 1, r.6
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mtibatu 1, r.6
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mtibatl 2, r.6
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mtibatu 2, r.6
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mtibatl 3, r.6
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mtibatu 3, r.6
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setsr: rlwimi r.11, r.10, 28, 0, 3 // Shift segment reg. # to bits 0-3
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or r.12, r.9, r.10 // Segment register value 0x87f000sr
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mtsrin r.12, r.11
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addic. r.10, r.10, -1 // Next segment register
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bne setsr
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mtsr 0, r.9 // Set the last segment register
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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sync // quiet the machine down
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sync
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sync
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sync
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stb r.6, 0(r.7) // switch memory
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eieio // flush io
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sync
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sync
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sync
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sync
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mtspr HID0, r.5 // switch ends on the cpu
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sync
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sync
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sync
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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addi r.0, r.1, 0x138 // same both ways
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rfi // head off into the reset handler
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end_little:
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addi r.0, r.1, 0x138 // we never get here
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addi r.0, r.1, 0x138
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b $
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//
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// For the 603 (and hopefully other) processor(s) things are a little
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// easier because little-endianness is controlled by the MSR. We still
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// have to change memory seperately so we still want code from the memory
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// switch thru the cpu switch in cache.
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//
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// When we get here
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// r.4 contains the address of the ROM resident Machine Reset
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// handler.
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// r.5 contains HID0 present value.
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// r.6 contains 0.
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// r.7 contains the port address (real) used to switch memory
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// endianness.
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// r.8 contains MSR present value.
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// r.9 contains the physical address of "here"
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// r.31 contains the processor type
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not_601:
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cmpwi r.31, 3 // is 603?
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beq is_603
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cmpwi r.31, 6 // is 603+?
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beq is_603
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cmpwi r.31, 7 // is 603ev?
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beq is_603
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cmpwi cr.2, r.31, 4 // is 604?
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cmpwi cr.3, r.31, 9 // is 604+?
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b not_603
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//
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// 603 I-Cache is invalidated by setting ICFI in HID0. Unlike
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// the 604, this bit is not self clearing.
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//
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is_603: rlwinm r.5, r.5, 0, ~H0_603_DCE// turn off D-cache
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rlwinm r.10, r.5, 0, ~H0_603_ICE// turn off I-cache
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ori r.10, r.10, H0_603_ICFI // I-Cache Flash Invalidate
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ori r.5, r.5, H0_603_ICE // I-cache enable
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isync
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mtspr HID0, r.10 // invalidate/disable
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mtspr HID0, r.5 // enable
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b common_6034
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not_603:
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beq cr.2, is_604
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// bne not_604
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// Note: the above branch is commented out because we don't
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// currently have any other options,... 620 will probably
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// be different.
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is_604: tlbsync // wait all processor tlb invalidate
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//
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// 604 caches must be enabled in order to be invalidated. It
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// is acceptable to enable and invalidate with the same move
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// to hid0. The data cache will be left disabled, the instruction
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// cache enabled.
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//
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ori r.5, r.5, H0_604_DCE | H0_604_ICE
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ori r.10, r.5, H0_604_DCIA | H0_604_ICIA
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rlwinm r.5, r.5, 0, ~H0_604_DCE
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rlwinm r.5, r.5, 0, ~H0_604_DCIA
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rlwinm r.5, r.5, 0, ~H0_604_ICIA
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mtspr HID0, r.10 // enable + invalidate
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mtspr HID0, r.5 // disable data cache
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rlwinm r.10, r.5, 0, ~H0_604_ICE // disable i-cache later
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// b common_6034 // join common code
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//
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// The following is common to both 603 and 604
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//
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common_6034:
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//
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// MSR bits ILE and POW must be disabled via mtmsr as rfi only moves
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// the least significant 16 bits into the MSR.
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//
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rlwinm r.8, r.8, 0, ~MASK_SPR(MSR_DR,1) // -= Data Relocation
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rlwinm r.8, r.8, 0, ~MASK_SPR(MSR_POW,1) // -= Power Management
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rlwinm r.8, r.8, 0, ~MASK_SPR(MSR_ILE,1) // -= Interrupt Little Endian
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sync
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mtmsr r.8
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sync
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//
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// Try to issue a hard reset. If this fails, the fall
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// thru and continue to manually return to firmware.
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//
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addi r.5, r.0, 0xFF // All ones
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stb r.5, 0(r.7) // Reset the System
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sync
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sync
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sync
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sync
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//
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// Continue returning to firmware...
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//
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//
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// Use an rfi to switch to big-endian, untranslated, interrupt prefix on
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// with a target address in the nice harmless pallindromic code below.
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// use another rfi to branch to the rom resident reset handler.
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//
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li r.8, MASK_SPR(MSR_ME,1) | MASK_SPR(MSR_IP,1)
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addi r.9, r.9, uncached_6034-here
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mtsrr1 r.8 // state = Machine Check Enabled
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bl here2
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here2: mflr r.28
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rlwinm r.28, r.28, 0, 0x7fffffff // convert address to physical
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lwz r.29, endofroutine - here2(r.28)
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mtsrr0 r.9 // rfi to uncached_6034
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b jumpswap
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memoryswap:
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ori r.8, r.28, 0
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addi r.8, r.8, swapend - uncached_6034
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addis r.15, r.15, 0
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addi r.9, 0, 0
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addi r.15, r.15, swapend - uncached_6034
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addis r.14, 0, 0
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addi r.14, 0, 4
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swaploop:
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lwz r.11, 0(r.8)
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lwz r.12, 4(r.8)
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stwbrx r.11, r.14, r.8
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stwbrx r.12, 0, r.8
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addi r.8, r.8, 8
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subi r.15, r.15, 8
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cmpi 0, 0, r.15, 0
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bgt swaploop
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jumpswap:
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//
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// The following bizzareness is to ensure that the memory switch thru
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// the disabling of cache is in cache. There is less than 32 bytes so
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// they must be part of either the cache line we are currently in, or
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// the one at the target of the branch. Therefore, branching over them,
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// doing a little and branching back to them should be enough to enure
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// they're cache resident.
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//
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b fill_icache
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goto_bigendian:
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stb r.6, 0(r.7) // switch memory
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sync
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sync
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sync
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sync
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sync
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lwz r.30, endofroutine - here2(r.28)
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cmp 0, 0, r.29, r.30
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beq memoryswap
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rfi
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fill_icache:
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isync
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sync // complete everything!
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b goto_bigendian
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
.globl uncached_6034
|
||
|
|
.long uncached_6034
|
||
|
|
|
||
|
|
uncached_6034:
|
||
|
|
.big_endian // out of cache fetches must be
|
||
|
|
// assembled in same mode as processor
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
addi r.0, r.1, 0x138 // same both ways
|
||
|
|
mtsrr0 r.4 // rfi target = 0xfff00100
|
||
|
|
mtspr HID0, r.10 // DISABLE CACHING
|
||
|
|
mtibatl 0, r.6 // invalidate/clear all bats
|
||
|
|
mtibatu 0, r.6
|
||
|
|
mtibatl 1, r.6
|
||
|
|
mtibatu 1, r.6
|
||
|
|
mtibatl 2, r.6
|
||
|
|
mtibatu 2, r.6
|
||
|
|
mtibatl 3, r.6
|
||
|
|
mtibatu 3, r.6
|
||
|
|
mtdbatl 0, r.6
|
||
|
|
mtdbatu 0, r.6
|
||
|
|
mtdbatl 1, r.6
|
||
|
|
mtdbatu 1, r.6
|
||
|
|
mtdbatl 2, r.6
|
||
|
|
mtdbatu 2, r.6
|
||
|
|
mtdbatl 3, r.6
|
||
|
|
mtdbatu 3, r.6
|
||
|
|
mtsr 0, r.6
|
||
|
|
mtsr 1, r.6
|
||
|
|
mtsr 2, r.6
|
||
|
|
mtsr 3, r.6
|
||
|
|
mtsr 4, r.6
|
||
|
|
mtsr 5, r.6
|
||
|
|
mtsr 6, r.6
|
||
|
|
mtsr 7, r.6
|
||
|
|
mtsr 8, r.6
|
||
|
|
mtsr 9, r.6
|
||
|
|
mtsr 10, r.6
|
||
|
|
mtsr 11, r.6
|
||
|
|
mtsr 12, r.6
|
||
|
|
mtsr 13, r.6
|
||
|
|
mtsr 14, r.6
|
||
|
|
mtsr 15, r.6
|
||
|
|
rfi // go to machine reset handler
|
||
|
|
// never get here
|
||
|
|
.little_endian
|
||
|
|
endofroutine:
|
||
|
|
sync
|
||
|
|
.globl swapend
|
||
|
|
.long swapend
|
||
|
|
swapend:
|
||
|
|
|
||
|
|
LEAF_EXIT(HalpPowerPcReset)
|