299 lines
10 KiB
C
299 lines
10 KiB
C
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#ident "@(#) NEC cirrus.h 1.2 94/11/21 13:58:39"
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/* #pragma comment(exestr, "@(#) NEC(MIPS) cirrus.h 1.7 94/02/03 18:58:17" ) */
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/* #pragma comment(exestr, "@(#) NEC(MIPS) cirrus.h 1.6 94/01/28 11:50:02" ) */
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/* #pragma comment(exestr, "@(#) NEC(MIPS) cirrus.h 1.4 93/10/29 12:25:02" ) */
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/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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cirrus.h
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Abstract:
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This module contains the definitions for the code that implements the
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Cirrus Logic VGA 6410/6420/542x device driver.
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Environment:
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Kernel mode
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Notes:
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This module based on Cirrus Minport Driver. And modify for R96 MIPS
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R4400 HAL Cirrus display initialize.
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Revision History:
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--*/
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/*
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* M001 1993.19.28 A. Kuriyama @ oa2
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*
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* - Modify for R96 MIPS R4400 HAL
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*
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* Delete : Miniport Driver Interface
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*
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* M002 1994.2.2 A. Kuriyama @ oa2
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* - Bug fix
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*
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* Modify : Video Memory Physical Address
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*
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*
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* Revision History in Cirrus Miniport Driver as follows:
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*
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* L001 1993.10.15 Kuroki
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*
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* - Modify for R96 MIPS R4400 *
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* Delete : Micro channel Bus Initialize.
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* VDM & Text, Fullscreen mode support.
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* Banking routine.
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* CL64xx Chip support.
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* 16-color mode.
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*
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* Add : Liner Addressing.
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*
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* L002 1993.10.21 Kuroki
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*
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* - Warniing clear
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*
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***************************************************************
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*
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* S001 1994.06.06 T.Samezima
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*
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* - Modify for R98 MIPS R4400
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*
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* Change : LA_MASK
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*
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* S002 '94.11/21 T.Samezima
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* Chg invalid S001
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*
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*/
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//
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// Change Ushort to Uchar, because R96 is mips machine.
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//
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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/* START L001 */
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/* START M002 */
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#define LA_MASK 0xe // S001, S002
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/* END M002 */
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#define MEM_VGA (LA_MASK << 20)
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#define MEM_VGA_SIZE 0x100000
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/* END L001 */
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//
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// Port definitions for filling the ACCSES_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// VGA port-related definitions.
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//
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//
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// VGA register definitions
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//
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// ports in monochrome mode
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#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x010
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#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x0015 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x0017 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x001F // and Data registers
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// ports in color mode
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#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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// toggle in color mode
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//
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// VGA indexed register indexes.
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//
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// CL-GD542x specific registers:
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//
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#define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
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#define IND_CL_SCRATCH_PAD 0x0A // index in Seq of POST scratch pad
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#define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
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// in CRTC
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Indices for type of memory mapping; used in ModesVGA[], must match
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// MemoryMap[].
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//
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typedef enum _VIDEO_MEMORY_MAP {
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MemMap_Mono,
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MemMap_CGA,
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MemMap_VGA
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} VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
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//
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// For a mode, the type of banking supported. Controls the information
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// returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
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//
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typedef enum _BANK_TYPE {
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NoBanking = 0,
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NormalBanking,
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PlanarHCBanking
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} BANK_TYPE, *PBANK_TYPE;
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#define CL6410 0x0001
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#define CL6420 0x0002
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#define CL542x 0x0004
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// bitfields for the DisplayType
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#define crt 0x0001
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#define panel 0x0002
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#define simulscan 0x0004 // this means both, but is unused for now.
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