197 lines
5.8 KiB
ArmAsm
197 lines
5.8 KiB
ArmAsm
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// "@(#) NEC cacherr.s 1.2 94/10/17 11:02:44"
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// TITLE("Cache Error Handling")
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//++
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//
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// Copyright (c) 1993-1994 Microsoft Corporation
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//
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// Module Name:
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//
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// cacherr.s
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//
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// Abstract:
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//
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// This module implements cache error handling. It is entered in KSEG1
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// directly from the cache error vector wiht ERL set in the processor
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// state.
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//
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// N.B. All the code in this routine MUST run in KSEG1 and reference
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// data only in KSEG1 until which time as any cache errors have
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// been corrected.
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//
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// N.B. This routine is NOT COMPLETE. All cache errors result in a
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// soft reset.
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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//
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//--
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#include "halmips.h"
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//
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// Define local save area for register state.
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//
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.data
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SavedAt:.space 4 // saved integer register at - a3
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SavedV0:.space 4 //
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SavedV1:.space 4 //
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SavedA0:.space 4 //
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SavedA1:.space 4 //
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SavedA2:.space 4 //
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SavedA3:.space 4 //
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SBTTL("Cache Error Handling")
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//++
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//
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// VOID
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// HalpCacheErrorRoutine (
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// VOID
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// )
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//
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// Routine Description:
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//
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// This function is entered from the cache error vector executing
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// in KSEG1. If the error is a single bit ECC error in the second
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// level data cache or the error is in the primary instruction cache,
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// then the error is corrected and execution is continued. Otherwise,
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// a fatal system error has occured and control is transfered to the
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// soft reset vector.
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//
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// N.B. No state has been saved when this routine is entered.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpCacheErrorRoutine)
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//
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// Save volatile registers needed to fix cache error.
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//
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.set noreorder
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.set noat
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la k0,SavedAt // get address of register save area
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li k1,KSEG1_BASE // convert address of KSEG1 address
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or k0,k0,k1 //
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sw AT,0(k0) // save registers AT - a3
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sw v0,4(k0) //
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sw v1,8(k0) //
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sw a0,12(k0) //
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sw a1,16(k0) //
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sw a2,20(k0) //
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//
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// Get the current processor state and cache error register, and check
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// if the error can be corrected.
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//
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mfc0 v0,psr // get current processor state
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mfc0 v1,cacheerr // get cache error state
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.set at
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.set reorder
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//
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// ****** temp ******
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//
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// The following code is temporary and will be removed when full cache
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// error support is included.
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//
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// ****** temp ******
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//
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b SoftReset // ****** all error soft rest
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//
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// If the EXL bit is set in the processor state, then the error is not
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// recoverable because the EXL bit may be erroneously set (errata) and
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// it cannot be determined whether is should or should not be set, e.g.,
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// the exact addresses ranges over which EXL might be correctly set are
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// not verifiable. Also, k0 and k1 are destroyed before they are saved
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// and are used by the exception handling code (there is no way to save
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// a register in noncached memory wihtout the use of a register).
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//
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sll a0,v0,31 - PSR_EXL // shift EXL bit in sign
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bltz a0,SoftReset // if ltz, error not correctable
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//
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// If the error occured on the SysAd bus, then the error is not correctable.
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//
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sll a0,v1,31 - CACHEERR_EE // shift EE bit into sign
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bltz a0,SoftReset // if ltz, error not correctable
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//
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// Determine whether the error is in the instruction or data cache.
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//
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sll a0,v1,31 - CACHEERR_ER // shift ER bit into sign
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bgez a0,IcacheError // if gez, instruction cache error
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//
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// The error occured in the data cache.
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//
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// If the error is a data error in the primary cache, then the error
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// is not correctable since the cache line dirty bit is included in
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// the parity calculation and therefore may be wrong.
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//
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DcacheError: //
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sll a0,v1,31 - CACHEERR_EC // shift EC bit into sign
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bgez a0,SoftReset // if gez, error in primary cache
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b ExitError // exit error
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//
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// The error occured in the instruction cache.
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//
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// If the error occured in the secondary data cache, then the error is not
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// correctable since there is not secondary instruciton cache.
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//
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IcacheError: //
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sll a0,v1,31 - CACHEERR_EC // shift EC bit into sign
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bltz a0,SoftReset // if ltz, error in secondary cache
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//
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// The cache error has been corrected - restore register state and continue
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// execution.
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//
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ExitError: //
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.set noreorder
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.set noat
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la k0,SavedAt // get address of register save area
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li k1,KSEG1_BASE // convert address of KSEG1 address
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or k0,k0,k1 //
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lw AT,0(k0) // restore registers AT - a3
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lw v0,4(k0) //
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lw v1,8(k0) //
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lw a0,12(k0) //
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lw a1,16(k0) //
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lw a2,20(k0) //
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eret //
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.set at
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.set reorder
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//
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// Cache error cannot be corrected - transfer control to soft reset vector.
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//
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SoftReset: //
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la k0,SOFT_RESET_VECTOR // get address of soft reset vector
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j k0 // perform a soft reset
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.end HalpCacheErrorRoutine
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