523 lines
9.6 KiB
ArmAsm
523 lines
9.6 KiB
ArmAsm
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// "@(#) NEC r98int.s 1.14 95/06/19 11:35:43"
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// TITLE("Interrupts service routine")
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//++
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//
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// Copyright (c) 1994 Kobe NEC Software
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//
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// Module Name:
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//
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// r98int.s
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//
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// Abstract:
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//
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//
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// Author:
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//
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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//
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// S001 '94.6/03 T.Samezima
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//
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// Del iRSF interrupt clear
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//
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//**************************************************************
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//
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// S002 94.6/13 T.Samezima
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//
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// Del Compile err
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//
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//**************************************************************
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//
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// S003 94.7/15 T.Samezima
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//
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// Chg change register access from 8byte access to 4byte access
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//
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//**************************************************************
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//
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// S004 94.7/20 T.Samezima
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//
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// Del Compile err
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// K001 94/10/11 N.Kugimoto
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// Add.chg HalpNmiHandler() from r98hwsup.c and chg
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//
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// S005 94/01/15 T.Samezima
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// Add HalpReadPhysicalAddr()
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//
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// S006 94/01/24 T.Samezima
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// Add HalpWritePhysicalAddr(),HalpReadAndWritePhysicalAddr(),
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//
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// S007 94/03/10-17 T.Samezima
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// Chg HalpNMIHandler().
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//
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// A002 1995/6/17 ataka@oa2.kb.nec.co.jp
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// - resolve compile error or logic error?
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//--
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#include "halmips.h"
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#include "r98def.h"
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SBTTL("Timer Interrupt")
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//++
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//
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// Routine Description:
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//
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// This routine is enterd as the result of an timer interrupt.
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//
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// Argments:
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//
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// s8 - Supplies a pointer to a trap frame.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpTimerDispatch)
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move a0,s8
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j HalpTimerScDispatch
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.end HalpTimerDispatch
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SBTTL("Read Large Register")
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//++
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//
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// Routine Description:
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//
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// This routine is read of large register
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//
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// Argments:
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//
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// a0 - Virtual address
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//
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// a1 - pointer to buffer of upper 32bit large register
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//
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// a2 - pointer to buffer of lower 32bit large register
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpReadLargeRegister)
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// Start S003
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#if 0
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DISABLE_INTERRUPTS(t7) // disable interrupts
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mfc1 t0,f0 // save f0 register
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mfc1 t1,f1 // save f1 register
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ldc1 f0,0x0(a0) // read register
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mfc1 t2,f0 // get register(upper)
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mfc1 t3,f1 // get register(lower)
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#endif
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lw t2,0x0(a0) // get register(upper)
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lw t3,0x4(a0) // get register(lower)
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sw t2,0x0(a1) // set upper register value
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sw t3,0x0(a2) // set lower register value
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#if 0
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mtc1 t0,f0 // restore f0 register
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mtc1 t1,f1 // restore f1 register
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sync //
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ENABLE_INTERRUPTS(t7) // enable interrupts
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#endif
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// End S003
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j ra // return
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.end HalpReadLargeRegister
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SBTTL("Write Large Register")
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//++
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//
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// Routine Description:
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//
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// This routine is write of large register
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//
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// Argments:
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//
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// a0 - Virtual address
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//
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// a1 - pointer to value of upper 32bit of large register
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//
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// a2 - pointer to value of lower 32bit of large register
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpWriteLargeRegister)
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// Start S003
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#if 0
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DISABLE_INTERRUPTS(t7) // disable interrupts
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mfc1 t0,f0 // save f0 register
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mfc1 t1,f1 // save f1 register
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#endif
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lw t2,0x0(a1) // load upper register value
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lw t3,0x0(a2) // load lower register value
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sw t2,0x0(a0) // set upper register value
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sw t3,0x4(a0) // set lower register value
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#if 0
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mtc1 t2,f0 // set register(upper)
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mtc1 t3,f1 // set register(lower)
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sdc1 f0,0x0(a0) // write register
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mtc1 t0,f0 // restore f0 register
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mtc1 t1,f1 // restore f1 register
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#endif
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sync //
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// ENABLE_INTERRUPTS(t7) // enable interrupts
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// End S003
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j ra // return
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.end HalpWriteLargeRegister
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SBTTL("Read Cause Register")
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//++
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// S005
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// Routine Description:
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//
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// This routine is get of cause register
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//
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// Argments:
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//
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// None.
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//
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// Return Value:
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//
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// cause rezister value.
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//
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//--
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LEAF_ENTRY(HalpGetCause)
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READ_CAUSE_REGISTER(v0)
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j ra // return
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.end HalpGetCause
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// S005 vvv
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SBTTL("Read Physical Address")
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//++
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//
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// Routine Description:
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//
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// This routine is read of physical address.
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//
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// Argments:
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//
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// a0 - Physical address
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//
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// Return Value:
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//
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// read data.
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//
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//--
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LEAF_ENTRY(HalpReadPhysicalAddr)
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li t1,0x90000000
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.set noreorder
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.set noat
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li t6,1 << PSR_CU1 // disable interrupt
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ori t6,t6,1 << PSR_KX // use 64bit address mode
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mfc0 t7,psr //
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mtc0 t6,psr //
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nop
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nop
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.set at
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.set reorder
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and t0,zero,zero
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dsll t0,t1,32 // shift entry address to upper 32-bits
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or t0,t0,a0 // make access address
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lw v0,0(t0)
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.set noreorder
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.set noat
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mtc0 t7,psr // enable interrupt
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nop
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.set at
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.set reorder
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j ra // return
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.end HalpReadPhysicalAddress
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// S005 ^^^
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// S006 vvv
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SBTTL("Write Physical Address")
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//++
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//
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// Routine Description:
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//
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// This routine is Write of physical address.
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//
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// Argments:
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//
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// a0 - Physical address
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//
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// a1 - Write Data
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpWritePhysicalAddr)
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li t1,0x90000000
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.set noreorder
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.set noat
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li t6,1 << PSR_CU1 // disable interrupt
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ori t6,t6,1 << PSR_KX // use 64bit address mode
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mfc0 t7,psr //
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mtc0 t6,psr //
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nop
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nop
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.set at
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.set reorder
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and t0,zero,zero
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dsll t0,t1,32 // shift entry address to upper 32-bits
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or t0,t0,a0 // make access address
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sw a1,0(t0)
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.set noreorder
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.set noat
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mtc0 t7,psr // enable interrupt
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nop
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.set at
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.set reorder
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j ra // return
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.end HalpWritePhysicalAddress
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SBTTL("Read And Write Physical Address")
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//++
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//
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// Routine Description:
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//
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// This routine is read and write of physical address.
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//
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// Argments:
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//
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// a0 - Physical address
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//
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// Return Value:
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//
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// read data.
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//
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//--
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LEAF_ENTRY(HalpReadAndWritePhysicalAddr)
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li t1,0x90000000
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.set noreorder
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.set noat
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li t6,1 << PSR_CU1 // disable interrupt
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ori t6,t6,1 << PSR_KX // use 64bit address mode
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mfc0 t7,psr //
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mtc0 t6,psr //
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nop
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nop
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.set at
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.set reorder
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and t0,zero,zero
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dsll t0,t1,32 // shift entry address to upper 32-bits
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or t0,t0,a0 // make access address
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lw v0,0(t0)
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sw v0,0(t0)
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.set noreorder
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.set noat
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mtc0 t7,psr // enable interrupt
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nop
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.set at
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.set reorder
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j ra // return
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.end HalpReadAndWritePhysicalAddress
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// S006 ^^^
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SBTTL("HalpNmiHandler")
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//++
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// K001
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// Routine Description:
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//
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// This routine is reset status Register on NMI.
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// Return from this function EIF Interrupt Occur!!
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// Argments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpNmiHandler)
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.set noat
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// S007 vvv
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//
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// reset NMIR register, set NMI flag and save CPU register.
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//
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li k0,0xb9980308 // Set STSR address
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li k1,0x08080000 // Disable NMI
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sw k1,0x0(k0) //
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la k0,HalpNMIFlag // set NMI flag address
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// li k1,0xa0000000 // KSEG1_ACCESS
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// or k0,k0,k1 //
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li k1,0xb9980030 // set NMIR address
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lw k1,(k1) // get NMIR register
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addi k1,k1,1 // set NMI flag
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sw k1,(k0) //
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li k1,0xb8c80000 // Reset NMI
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sb zero,0x0(k1) //
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#if 1
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// lw k0,KiPcr + PcPrcb(zero) // get current processor block address
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// la k1,HalpNMIBuf // get performance counter address
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// lbu k0,PbNumber(k0) // get processor number
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// sll k0,k0,7 // compute address of nmi buffer
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// addu k0,k0,k1 //
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li k0,0xb9980300 // get CNFG Register Addr of PMC
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li k1,0x00007000 // Mask Node Of CPU0-CPU3
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lw k0 ,0x0(k0) // get value of etc of PMC
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and k0,k0,k1 // get value of NODE
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la k1,HalpNMIBuf // get performance counter address
|
||
|
|
srl k0,k0,5 // shift right 7 bit for offset
|
||
|
|
addu k0,k0,k1 // compute address of nmi buffer
|
||
|
|
|
||
|
|
// sw at,0x0(k0) // register save.
|
||
|
|
sw v0,0x4(k0) //
|
||
|
|
sw v1,0x8(k0) //
|
||
|
|
sw a0,0xc(k0) //
|
||
|
|
sw a1,0x10(k0) //
|
||
|
|
sw a2,0x14(k0) //
|
||
|
|
sw a3,0x18(k0) //
|
||
|
|
sw t0,0x1c(k0) //
|
||
|
|
sw t1,0x20(k0) //
|
||
|
|
sw t2,0x24(k0) //
|
||
|
|
sw t3,0x28(k0) //
|
||
|
|
sw t4,0x2c(k0) //
|
||
|
|
sw t5,0x30(k0) //
|
||
|
|
sw t6,0x34(k0) //
|
||
|
|
sw t7,0x38(k0) //
|
||
|
|
sw t8,0x3c(k0) //
|
||
|
|
sw t9,0x40(k0) //
|
||
|
|
sw gp,0x44(k0) //
|
||
|
|
sw sp,0x48(k0) //
|
||
|
|
sw s8,0x4c(k0) //
|
||
|
|
sw ra,0x50(k0) //
|
||
|
|
|
||
|
|
.set noreorder
|
||
|
|
|
||
|
|
mfc0 k1,psr //
|
||
|
|
sw k1,0x54(k0) //
|
||
|
|
mfc0 k1,cause //
|
||
|
|
sw k1,0x58(k0) //
|
||
|
|
mfc0 k1,epc //
|
||
|
|
sw k1,0x5c(k0) //
|
||
|
|
mfc0 k1,errorepc //
|
||
|
|
sw k1,0x60(k0) //
|
||
|
|
|
||
|
|
.set reorder
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
li k0,0xb9980038 // set NMIRST address
|
||
|
|
li k1,0x8 // it is DUMP Key NMI
|
||
|
|
sw k1,(k0) // reset nmi
|
||
|
|
.set noreorder // A002
|
||
|
|
nop
|
||
|
|
//
|
||
|
|
// This is a test code.
|
||
|
|
// We must clear BEV bit of psr register.
|
||
|
|
//
|
||
|
|
|
||
|
|
mfc0 k1,psr // get psr
|
||
|
|
li k0,0xffafffff // BEV bit clear
|
||
|
|
nop // fill
|
||
|
|
and k1,k1,k0 //
|
||
|
|
nop //
|
||
|
|
mtc0 k1,psr // set psr
|
||
|
|
nop // fill
|
||
|
|
nop //
|
||
|
|
nop //
|
||
|
|
|
||
|
|
// li k0,0xb9980308 // Read STSR Register
|
||
|
|
// lw k1,(k0) //
|
||
|
|
// or k1,k1,0x80800000// make eif
|
||
|
|
// sw k1,(k0) //
|
||
|
|
// nop
|
||
|
|
|
||
|
|
li k0,0xb9980100 // IntIR Register addr
|
||
|
|
li k1,0x0082f000 // Do eif to CPU0 only.
|
||
|
|
sw k1,(k0) //
|
||
|
|
|
||
|
|
nop
|
||
|
|
eret // return to errorepc
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
eret // errata
|
||
|
|
nop
|
||
|
|
#if 0
|
||
|
|
mfc0 k0,epc // As if behave No Nmi
|
||
|
|
nop
|
||
|
|
nop
|
||
|
|
j k0 // As if behave No Nmi.
|
||
|
|
#endif // I Hope EIF Interrut
|
||
|
|
// Occur later!!.
|
||
|
|
//
|
||
|
|
// S007 ^^^
|
||
|
|
|
||
|
|
.set at
|
||
|
|
.set reorder
|
||
|
|
|
||
|
|
|
||
|
|
.end HalpNmiHandler
|
||
|
|
|