167 lines
3.5 KiB
C
167 lines
3.5 KiB
C
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/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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j4flshio.c
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Abstract:
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This module implements the system dependent kernel function to flush
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the data cache for I/O transfers on a MIPS R4000 Jazz system.
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Author:
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David N. Cutler (davec) 24-Apr-1991
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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VOID
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HalFlushIoBuffers (
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IN PMDL Mdl,
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IN BOOLEAN ReadOperation,
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IN BOOLEAN DmaOperation
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)
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/*++
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Routine Description:
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This function flushes the I/O buffer specified by the memory descriptor
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list from the data cache on the current processor.
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Arguments:
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Mdl - Supplies a pointer to a memory descriptor list that describes the
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I/O buffer location.
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ReadOperation - Supplies a boolean value that determines whether the I/O
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operation is a read into memory.
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DmaOperation - Supplies a boolean value that determines whether the I/O
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operation is a DMA operation.
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Return Value:
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None.
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--*/
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{
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ULONG CacheSegment;
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ULONG Length;
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ULONG Offset;
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KIRQL OldIrql;
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PULONG PageFrame;
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ULONG Source;
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//
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// The Jazz R4000 uses a write back data cache and, therefore, must be
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// flushed on reads and writes.
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//
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// If the length of the I/O operation is greater than the size of the
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// data cache, then sweep the entire data cache. Otherwise, export or
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// purge individual pages from the data cache as appropriate.
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//
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Offset = Mdl->ByteOffset & PCR->DcacheAlignment;
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Length = (Mdl->ByteCount +
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PCR->DcacheAlignment + Offset) & ~PCR->DcacheAlignment;
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if ((Length > PCR->FirstLevelDcacheSize) &&
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(Length > PCR->SecondLevelDcacheSize)) {
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if ((ReadOperation != FALSE) &&
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((Mdl->MdlFlags & MDL_IO_PAGE_READ) != 0)) {
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HalSweepDcache();
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HalSweepIcache();
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}
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} else {
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//
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// Export or purge the specified pages from the data cache and
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// instruction caches as appropriate.
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//
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// Compute the number of pages to flush and the starting MDL page
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// frame address.
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//
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Offset = Mdl->ByteOffset & ~PCR->DcacheAlignment;
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PageFrame = (PULONG)(Mdl + 1);
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Source = ((ULONG)(Mdl->StartVa) & 0xfffff000) | Offset;
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//
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// Export or purge the specified page segments from the data and
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// instruction caches as appropriate.
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//
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do {
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if (Length >= (PAGE_SIZE - Offset)) {
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CacheSegment = PAGE_SIZE - Offset;
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} else {
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CacheSegment = Length;
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}
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if (ReadOperation == TRUE) {
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if (DmaOperation == FALSE) {
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if ((Mdl->MdlFlags & MDL_IO_PAGE_READ) != 0) {
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HalFlushDcachePage((PVOID)Source, *PageFrame, CacheSegment);
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}
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}
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if ((Mdl->MdlFlags & MDL_IO_PAGE_READ) != 0) {
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HalPurgeIcachePage((PVOID)Source, *PageFrame, CacheSegment);
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}
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}
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PageFrame += 1;
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Length -= CacheSegment;
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Offset = 0;
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Source += CacheSegment;
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} while(Length != 0);
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}
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return;
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}
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ULONG
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HalGetDmaAlignmentRequirement (
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VOID
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)
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/*++
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Routine Description:
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This function returns the alignment requirements for DMA transfers on
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host system.
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Arguments:
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None.
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Return Value:
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The DMA alignment requirement is returned as the fucntion value.
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--*/
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{
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return PCR->DcacheFillSize;
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}
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