609 lines
17 KiB
C
609 lines
17 KiB
C
/************************************************************************/
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/* */
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/* Driver Name: QL10WNT.SYS - NT Miniport Driver for QLogic ISP1020 */
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/* */
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/* Source File Name: QLISP.H */
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/* */
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/* Function: Internal data structures and C macros. */
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/* */
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/************************************************************************/
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/* */
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/* NOTICE */
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/* */
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/* COPYRIGHT 1994-1995 QLOGIC CORPORATION */
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/* ALL RIGHTS RESERVED */
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/* */
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/* This computer program is CONFIDENTIAL and a TRADE SECRET */
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/* of QLOGIC CORPORATION. The receipt or possesion of this */
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/* program does not convey any rights to reproduce or disclose */
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/* its contents, or to manufacture, use, or sell anything that */
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/* it may describe, in whole or in part, without the specific */
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/* written consent of QLOGIC CORPORATION. Any reproduction of */
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/* this program without the express written consent of QLOGIC */
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/* CORPORATION is a violation of the copyright laws and may */
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/* subject you to criminal prosecution. */
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/* */
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/************************************************************************/
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/* */
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/* Revision history: */
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/* */
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/* See QLISP.C module for driver revision history */
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/* */
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/************************************************************************/
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/**********************************************************************/
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/* Local defines and constants */
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/**********************************************************************/
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#define MAX_SUPPORTED_ADAPTERS 3 // maximum # of supported adapters
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#define NUM_SCSI_IDS 16
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#define NUM_SCSI_LUNS 8
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#define REQUEST_QUEUE_DEPTH 32
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#define RESPONSE_QUEUE_DEPTH 32
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#define MAX_SG_SEGMENTS 18 // max s/g segments (cmd entry + 2 cont entrys)
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#define MAX_CONT_ENTRYS 2 // max continuation entrys (2 = 18 s/g segments)
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#define WAIT_QUEUE_RETRY_CNT 1000
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#define CMD_RETRY_CNT 3
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#define DEFTIMEOUT 30 // default timeout (seconds)
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/************************************************************************/
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/* Macros */
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/************************************************************************/
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/**********************************************************************/
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/* Forward typedefs */
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/**********************************************************************/
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/************************************************************************/
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/* NOVRAM definitions */
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/************************************************************************/
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/* NOVRAM data structure */
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typedef struct _NOVRAM
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{
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UCHAR id[4]; /* "ISP " */
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UCHAR version;
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/* bits */
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UCHAR Fifo_Threshold :2; /* 0,1 */
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UCHAR Not_Used0 :1; /* 2 */
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UCHAR Host_Adapter_Enable :1; /* 3 */
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UCHAR Initiator_SCSI_Id :4; /* 4,5,6,7 */
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UCHAR Bus_Reset_Delay;
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UCHAR Retry_Count;
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UCHAR Retry_Delay;
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/* bits */
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UCHAR ASync_Data_Setup_Time :4; /* 0,1,2,3 */
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UCHAR REQ_ACK_Active_Negation :1; /* 4 */
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UCHAR DATA_Line_Active_Negation :1; /* 5 */
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UCHAR Data_DMA_Burst_Enable :1; /* 6 */
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UCHAR Command_DMA_Burst_Enable :1; /* 7 */
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UCHAR Tag_Age_Limit;
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/* bits */
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UCHAR Termination_Low_Enable :1; /* 0 */
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UCHAR Termination_High_Enable :1; /* 1 */
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UCHAR PCMC_Burst_Enable :1; /* 3 */
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UCHAR Sixty_MHz_Enable :1; /* 2 */
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UCHAR Not_Used1 :4;
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USHORT Selection_Timeout;
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USHORT Max_Queue_Depth;
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UCHAR Pad0[12];
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struct
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{ /*bit*/
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UCHAR Renegotiate_on_Error :1; /* 0 */
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UCHAR Stop_Queue_on_Check :1; /* 1 */
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UCHAR Auto_Request_Sense :1; /* 2 */
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UCHAR Tagged_Queuing :1; /* 3 */
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UCHAR Sync_Data_Transfers :1; /* 4 */
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UCHAR Wide_Data_Transfers :1; /* 5 */
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UCHAR Parity_Checking :1; /* 6 */
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UCHAR Disconnect_Allowed :1; /* 7 */
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UCHAR Execution_Throttle;
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UCHAR Sync_Period;
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/* bits */
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UCHAR Sync_Offset :4; /* 0,1,2,3 */
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UCHAR Device_Enable :1; /* 4 */
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UCHAR Not_Used2 :3; /* 5,6,7 */
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UCHAR Available0;
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UCHAR Available1;
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} Id[16];
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UCHAR Pad1[3];
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UCHAR Check_Sum;
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} NOVRAM, *PNOVRAM;
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/* Command values */
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#define NVRAM_START_BIT 4
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#define NVRAM_WRITE_OP (NVRAM_START_BIT+1)
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#define NVRAM_READ_OP (NVRAM_START_BIT+2)
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#define NVRAM_ERASE_OP (NVRAM_START_BIT+3)
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#define NVRAM_DELAY_COUNT 10
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/* NvRam Register bit values */
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#define NVRAM_DESELECT 0x00
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#define NVRAM_CLOCK 0x01
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#define NVRAM_SELECT 0x02
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#define NVRAM_DATA_OUT 0x04
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#define NVRAM_DATA_IN 0x08
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/* NvRam Parameter Defaults */
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#define OFF 0
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#define ON 1
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/* Host Adapter defaults */
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#define NVRAM_DEF_FIFO_THRESHOLD 2 /* 32 bytes */
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#define NVRAM_DEF_ADAPTER_ENABLE ON
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#define NVRAM_DEF_INITIATOR_SCSI_ID 7
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#define NVRAM_DEF_BUS_RESET_DELAY 3 /* 3 second */
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// Only 1 retry and no delay for NT driver (problem with NT 3.5 Disk Administrator)
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#define NVRAM_DEF_RETRY_COUNT 1
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#define NVRAM_DEF_RETRY_DELAY 0
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#define NVRAM_DEF_ASYNC_SETUP_TIME 6 /* 4 clock periods */
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#define NVRAM_DEF_REQ_ACK_ACTIVE_NEGATION ON
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#define NVRAM_DEF_DATA_ACTIVE_NEGATION ON
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#define NVRAM_DEF_DATA_DMA_BURST_ENABLE ON
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#define NVRAM_DEF_CMD_DMA_BURST_ENABLE ON
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#define NVRAM_DEF_TAG_AGE_LIMIT 8
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#define NVRAM_DEF_SELECTION_TIMEOUT 250 /* 250 ms */
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#define NVRAM_DEF_TERMINATION_LOW_ENABLE ON
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#define NVRAM_DEF_TERMINATION_HIGH_ENABLE ON
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#define NVRAM_DEF_PCMC_BURST_ENABLE OFF
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#define NVRAM_DEF_SIXTY_MHZ_ENABLE OFF
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/* Drive defaults */
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#define NVRAM_DEF_RENEGOTIATE_ON_ERROR ON
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#define NVRAM_DEF_STOP_QUEUE_ON_CHECK OFF
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#define NVRAM_DEF_AUTO_REQUEST_SENSE ON
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#define NVRAM_DEF_TAGGED_QUEUING ON
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#define NVRAM_DEF_SYNC_DATA_TRANSFERS ON
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#define NVRAM_DEF_WIDE_DATA_TRANSFERS ON
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#define NVRAM_DEF_PARITY_CHECKING ON
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#define NVRAM_DEF_DISCONNECT_ALLOWED ON
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#define NVRAM_DEF_SYNC_PERIOD 25
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#define NVRAM_DEF_SYNC_OFFSET 12
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#define NVRAM_DEF_DEVICE_ENABLE ON
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#define NVRAM_DEF_EXECUTION_THROTTLE 16
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#define NVRAM_DEF_MAX_QUEUE_DEPTH 256
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#define NVRAM_CONFIG_BURST_ENABLE 0x04
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/************************************************************************/
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/* PCI configuration definitions */
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/************************************************************************/
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typedef struct _PCI_CHIP_REGISTERS_M1 // Method 1
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{
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ULONG Config_Address;
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ULONG Config_Data;
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} PCI_CHIP_REGISTERS_M1, *PPCI_CHIP_REGISTERS_M1;
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#define PCI_MAXBUSNUM 256
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#define PCI_MAXDEVNUM 32
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#define PCI_CONFIG_ADDRESS 0xcf8
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#define PCI_CONFIG_DATA 0xcfc
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#define PCI_ENABLE_CONFIG 0x80000000
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#define PCI_DISABLE_CONFIG 0x00000000
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typedef struct _PCI_CHIP_REGISTERS // Method 2
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{
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UCHAR pci_config;
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} PCI_CHIP_REGISTERS, *PPCI_CHIP_REGISTERS;
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#define PCI_CONFIG 0xcf8
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#define PCI_ENABLE 0x80
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#define PCI_START 0xC000
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#define PCI_SLOT_CNT 16
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#define PCI_LAST 0xDFFF
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#define PCI_SIZE 0x100
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#define PCI_BEGIN_SEARCH (paddr_t)0xe0000
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#define PCI_END_SEARCH (paddr_t)0xfffff
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#define PCI_BIOS_VECT 0x6EFE00F0
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#define PCI_BIOS_INT 0x1A
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#define PCI_FUNCTION_ID 0xB100
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/* PCI Function List */
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#define PCI_BIOS_PRESENT 0xB101
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#define FIND_PCI_DEVICE 0xB102
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#define FIND_PCI_CLASS_CODE 0xB103
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#define GENERATE_SPECIAL_CYCLE 0xB106
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#define READ_CONFIG_BYTE 0xB108
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#define READ_CONFIG_WORD 0xB109
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#define READ_CONFIG_DWORD 0xB10A
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#define WRITE_CONFIG_BYTE 0xB10B
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#define WRITE_CONFIG_WORD 0xB10C
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#define WRITE_CONFIG_DWORD 0xB10D
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/* PCI Return Code List */
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#define SUCCESSFUL 0x00
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#define FUNC_NOT_SUPPORTED 0x81
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#define BAD_VENDOR_ID 0x83
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#define DEVICE_NOT_FOUND 0x86
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#define BAD_REGISTER_NUMBER 0x87
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/* Configuration space register definitions */
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typedef struct _PCI_REGS
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{
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USHORT Vendor_Id;
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#define QLogic_VENDOR_ID 0x1077
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USHORT Device_Id;
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#define QLogic_DEVICE_ID 0x1020
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USHORT Command;
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#define BUS_MASTER_ENABLE 0x0004
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USHORT Status;
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ULONG Rev_Id_Class_Code;
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UCHAR Cache_Line_Size;
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UCHAR Latency_Timer;
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UCHAR Header_Type;
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UCHAR BIST;
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ULONG IO_Base_Address;
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ULONG Memory_Base_Address;
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ULONG Base_Address_3;
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ULONG Base_Address_4;
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ULONG Base_Address_5;
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ULONG Base_Address_6;
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ULONG Reserved_1;
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ULONG Reserved_2;
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ULONG ROM_Base_Address;
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ULONG Reserved_3;
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ULONG Reserved_4;
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UCHAR Interrupt_Line;
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UCHAR Interrupt_Pin;
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UCHAR Minimum_Grant;
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UCHAR Maximum_Latency;
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UCHAR unused[192];
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} PCI_REGS, *PPCI_REGS;
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/****************************************************************/
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/* ISP firmware interface definitions */
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/****************************************************************/
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/*** Queue Entry structure ***/
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typedef struct _QueueEntry
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{
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UCHAR data[64];
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} QUEUE_ENTRY, *PQUEUE_ENTRY;
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/*** ENTRY HEADER structure ***/
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typedef struct
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{
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UCHAR entry_type;
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UCHAR entry_cnt;
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UCHAR sys_def_1;
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UCHAR flags;
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} ENTRY_HEADER;
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/* Entry Header Type Definitions */
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#define ET_COMMAND 1
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#define ET_CONTINUATION 2
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#define ET_STATUS 3
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#define ET_MARKER 4
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#define ET_EXTENDED_COMMAND 5
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/* Entry Header Flag Definitions */
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#define EF_CONTINUATION 0x01
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#define EF_BUSY 0x02
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#define EF_BAD_HEADER 0x04
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#define EF_BAD_PAYLOAD 0x08
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#define EF_ERROR_MASK (EF_BUSY | EF_BAD_HEADER | EF_BAD_PAYLOAD)
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/*** DATA SEGMENT structure ***/
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typedef struct
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{
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ULONG base;
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ULONG count;
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} DATA_SEG;
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/*** COMMAND ENTRY structure ***/
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typedef struct _CommandEntry
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{
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ENTRY_HEADER hdr;
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ULONG handle;
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UCHAR target_lun;
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UCHAR target_id;
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USHORT cdb_length;
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USHORT control_flags;
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USHORT reserved;
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USHORT time_out;
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USHORT segment_cnt;
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UCHAR cdb[12];
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DATA_SEG dseg[4];
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} COMMAND_ENTRY, *PCOMMAND_ENTRY;
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/* Command Entry Control Flag Definitions */
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#define CF_NO_DISCONNECTS 0x0001
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#define CF_HEAD_TAG 0x0002
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#define CF_ORDERED_TAG 0x0004
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#define CF_SIMPLE_TAG 0x0008
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#define CF_TARGET_ROUTINE 0x0010
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#define CF_READ 0x0020
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#define CF_WRITE 0x0040
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#define CF_NO_REQUEST_SENSE 0x0100
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/*** EXTENDED COMMAND ENTRY structure ***/
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typedef struct _ExtCommandEntry
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{
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ENTRY_HEADER hdr;
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ULONG handle;
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UCHAR target_lun;
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UCHAR target_id;
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USHORT cdb_length;
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USHORT control_flags;
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USHORT reserved;
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USHORT time_out;
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USHORT segment_cnt;
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UCHAR cdb[44];
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} EXT_COMMAND_ENTRY, *PEXT_COMMAND_ENTRY;
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/*** CONTINUATION ENTRY structure ***/
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typedef struct _ContinuationEntry
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{
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ENTRY_HEADER hdr;
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ULONG reserved;
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DATA_SEG dseg[7];
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} CONTINUATION_ENTRY, *PCONTINUATION_ENTRY;
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/*** MARKER ENTRY structure ***/
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typedef struct _MarkerEntry
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{
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ENTRY_HEADER hdr;
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ULONG reserved0;
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UCHAR target_lun;
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UCHAR target_id;
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UCHAR modifier;
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UCHAR reserved1;
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UCHAR reserved2[52];
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} MARKER_ENTRY, *PMARKER_ENTRY;
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/* Marker Entry Modifier Definitions */
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#define MM_SYNC_DEVICE 0
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#define MM_SYNC_TARGET 1
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#define MM_SYNC_ALL 2
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/*** STATUS ENTRY structure ***/
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typedef struct _StatusEntry
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{
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ENTRY_HEADER hdr;
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ULONG handle;
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USHORT scsi_status;
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USHORT completion_status;
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USHORT state_flags;
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USHORT status_flags;
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USHORT time;
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USHORT req_sense_length;
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ULONG residual;
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UCHAR reserved[8];
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UCHAR req_sense_data[32];
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} STATUS_ENTRY, *PSTATUS_ENTRY;
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/* Status Entry Completion Status Defintions */
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#define SCS_COMPLETE 0
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#define SCS_INCOMPLETE 1
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#define SCS_DMA_ERROR 2
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#define SCS_TRANSPORT_ERROR 3
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#define SCS_RESET_OCCURRED 4
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#define SCS_ABORTED 5
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#define SCS_TIMEOUT 6
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#define SCS_DATA_OVERRUN 7
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#define SCS_COMMAND_OVERRUN 8
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#define SCS_STATUS_OVERRUN 9
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#define SCS_BAD_MESSAGE 10
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#define SCS_NO_MESSAGE_OUT 11
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#define SCS_EXT_ID_FAILED 12
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#define SCS_IDE_MSG_FAILED 13
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#define SCS_ABORT_MSG_FAILED 14
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#define SCS_REJECT_MSG_FAILED 15
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#define SCS_NOP_MSG_FAILED 16
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#define SCS_PARITY_ERROR_MSG_FAILED 17
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#define SCS_DEVICE_RESET_MSG_FAILED 18
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#define SCS_ID_MSG_FAILED 19
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#define SCS_UNEXPECTED_BUS_FREE 20
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/* Status Entry State Flag Definitions */
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#define SS_GOT_BUS 0x0100
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#define SS_GOT_TARGET 0x0200
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#define SS_SENT_CDB 0x0400
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#define SS_TRANSFERRED_DATA 0x0800
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#define SS_GOT_STATUS 0x1000
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#define SS_GOT_SENSE 0x2000
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#define SS_TRANSFER_COMPLETE 0x4000
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/* Status Entry Status Flag Definitions */
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#define SST_DISCONNECT 0x0001
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#define SST_SYNCHRONOUS 0x0002
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#define SST_PARITY_ERROR 0x0004
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#define SST_BUS_RESET 0x0008
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#define SST_DEVICE_RESET 0x0010
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#define SST_ABORTED 0x0020
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#define SST_TIMEOUT 0x0040
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#define SST_NEGOTIATION 0x0080
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/* Mailbox Command Definitions */
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#define MBOX_CMD_LOAD_RAM 0x0001
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#define MBOX_CMD_EXECUTE_FIRMWARE 0x0002
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#define MBOX_CMD_WRITE_RAM_WORD 0x0004
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#define MBOX_CMD_READ_RAM_WORD 0x0005
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#define MBOX_CMD_MAILBOX_REGISTER_TEST 0x0006
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#define MBOX_CMD_VERIFY_CHECKSUM 0x0007
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#define MBOX_CMD_ABOUT_FIRMWARE 0x0008
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#define MBOX_CMD_INIT_REQUEST_QUEUE 0x0010
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#define MBOX_CMD_INIT_RESPONSE_QUEUE 0x0011
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#define MBOX_CMD_STOP_FIRMWARE 0x0014
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#define MBOX_CMD_ABORT 0x0015
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#define MBOX_CMD_ABORT_DEVICE 0x0016
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#define MBOX_CMD_ABORT_TARGET 0x0017
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#define MBOX_CMD_BUS_RESET 0x0018
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#define MBOX_CMD_START_QUEUE 0x001A
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#define MBOX_CMD_SET_INITIATOR_SCSI_ID 0x0030
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#define MBOX_CMD_SET_SELECTION_TIMEOUT 0x0031
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#define MBOX_CMD_SET_RETRY_COUNT 0x0032
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#define MBOX_CMD_SET_TAG_AGE_LIMIT 0x0033
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#define MBOX_CMD_SET_CLOCK_RATE 0x0034
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#define MBOX_CMD_SET_ACTIVE_NEGATION_STATE 0x0035
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#define MBOX_CMD_SET_ASYNC_DATA_SETUP_TIME 0x0036
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#define MBOX_CMD_SET_BUS_CONTROL_PARAMETERS 0x0037
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#define MBOX_CMD_SET_TARGET_PARAMETERS 0x0038
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#define MBOX_CMD_SET_DEVICE_QUEUE_PARAMETERS 0x0039
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#define MBOX_CMD_GET_FIRMWARE_STATUS 0x001F
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#define MBOX_CMD_GET_INITIATOR_SCSI_ID 0x0020
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#define MBOX_CMD_GET_SELECTION_TIMEOUT 0x0021
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#define MBOX_CMD_GET_RETRY_COUNT 0x0022
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#define MBOX_CMD_GET_TAG_AGE_LIMIT 0x0023
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#define MBOX_CMD_GET_CLOCK_RATE 0x0024
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#define MBOX_CMD_GET_ACTIVE_NEGATION_STATE 0x0025
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#define MBOX_CMD_GET_ASYNC_DATA_SETUP_TIME 0x0026
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#define MBOX_CMD_GET_BUS_CONTROL_PARAMETERS 0x0027
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#define MBOX_CMD_GET_TARGET_PARAMETERS 0x0028
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#define MBOX_CMD_GET_DEVICE_QUEUE_PARAMETERS 0x0029
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/* Mailbox Status Definitions */
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#define MBOX_STS_FIRMWARE_ALIVE 0x0000
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#define MBOX_STS_CHECKSUM_ERROR 0x0001
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#define MBOX_STS_SHADOW_LOAD_ERROR 0x0002
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#define MBOX_STS_BUSY 0x0004
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#define MBOX_STS_COMMAND_COMPLETE 0x4000
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#define MBOX_STS_INVALID_COMMAND 0x4001
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#define MBOX_STS_HOST_INTERFACE_ERROR 0x4002
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#define MBOX_STS_TEST_FAILED 0x4003
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#define MBOX_STS_COMMAND_ERROR 0x4005
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#define MBOX_STS_COMMAND_PARAMETER_ERROR 0x4006
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#define MBOX_ASTS_SCSI_BUS_RESET 0x8001
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#define MBOX_ASTS_SYSTEM_ERROR 0x8002
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#define MBOX_ASTS_REQUEST_TRANSFER_ERROR 0x8003
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#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR 0x8004
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#define MBOX_ASTS_REQUEST_QUEUE_WAKEUP 0x8005
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#define MBOX_ASTS_TIMEOUT_RESET 0x8006
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/****************************************************************/
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/* ISP Register Definitions */
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/****************************************************************/
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typedef struct _ISP_REGS
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{
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/* Bus interface registers */
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USHORT bus_id_low; /* 0000 */
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USHORT bus_id_high; /* 0002 */
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USHORT bus_config0; /* 0004 */
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USHORT bus_config1; /* 0006 */
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USHORT bus_icr; /* 0008 */
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USHORT bus_isr; /* 000A */
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USHORT bus_sema; /* 000C */
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USHORT NvRam_reg; /* 000E */
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|
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/* Skip over DMA Controller registers */
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|
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UCHAR not_used0[0x0060]; /* 0010-006F */
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|
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/* Mailbox registers */
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USHORT mailbox0; /* 0070 */
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USHORT mailbox1; /* 0072 */
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USHORT mailbox2; /* 0074 */
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USHORT mailbox3; /* 0076 */
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USHORT mailbox4; /* 0078 */
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USHORT mailbox5; /* 007A */
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|
|
|
/* Skip down to HCCR register */
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|
|
|
UCHAR not_used1[0x44]; /* 007C-00BF */
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|
|
|
/* Host Configuration and Control register */
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|
|
|
USHORT hccr; /* 00C0 */
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|
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UCHAR not_used3[0x3E]; /* 00C2-00FF */
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} ISP_REGS, *PISP_REGS;
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|
|
|
/* Bus Control Register Definitions */
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|
|
|
#define ICR_SOFT_RESET 0x0001
|
|
#define ICR_ENABLE_ALL_INTS 0x0002
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|
#define ICR_ENABLE_RISC_INT 0x0004
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#define ICR_DISABLE_ALL_INTS 0x0000
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|
|
|
/* Bus Interrupt Status Register Defintions */
|
|
|
|
#define BUS_ISR_RISC_INT 0x0004
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|
|
|
/* Bus Semaphore Register Definitions */
|
|
|
|
#define BUS_SEMA_LOCK 0x0001
|
|
#define BUS_SEMA_STATUS 0x0002
|
|
|
|
/* Host Command and Control Register Command Definitions */
|
|
|
|
#define HCCR_CMD_RESET 0x1000 /* Reset RISC */
|
|
#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
|
|
#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
|
|
#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
|
|
#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
|
|
#define HCCR_WRITE_BIOS_ENABLE 0x9000 /* Write BIOS enable */
|
|
|
|
/* Host Command and Control Register Status Definitions */
|
|
|
|
#define HCCR_HOST_INT 0x0080 /* R: Host interrupt set */
|
|
#define HCCR_RESET 0x0040 /* R: RISC reset in progress */
|
|
#define HCCR_PAUSE 0x0020 /* R: RISC paused */
|
|
|
|
/* ISP Product ID Definitions */
|
|
|
|
#define PROD_ID_1 0x4953
|
|
#define PROD_ID_2 0x0000
|
|
#define PROD_ID_2a 0x5020
|
|
#define PROD_ID_3 0x2020
|
|
#define PROD_ID_4 0x0001
|
|
|