503 lines
13 KiB
C
503 lines
13 KiB
C
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/*++
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Copyright (c) 1990-1995 Microsoft Corporation
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Module Name:
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D:\nt\private\ntos\ndis\aic5900\hw.h
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Abstract:
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Author:
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Kyle Brandon (KyleB)
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef __HW_H
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#define __HW_H
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//
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// New types and forward pointers...
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//
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typedef struct _HARDWARE_INFO HARDWARE_INFO, *PHARDWARE_INFO;
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typedef struct _ADAPTER_BLOCK ADAPTER_BLOCK, *PADAPTER_BLOCK;
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typedef struct _VC_BLOCK VC_BLOCK, *PVC_BLOCK;
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typedef struct _XMIT_SEG_CHANNEL XMIT_SEG_CHANNEL, *PXMIT_SEG_CHANNEL;
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typedef struct _SAR_INFO SAR_INFO, *PSAR_INFO;
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typedef struct _MIDWAY_XMIT_REGISTERS MIDWAY_XMIT_REGISTERS, *PMIDWAY_XMIT_REGISTERS;
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typedef struct _MIDWAY_REGISTERS MIDWAY_REGISTERS, *PMIDWAY_REGISTERS;
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typedef volatile ULONG HWUL, *PHWUL;
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typedef volatile UCHAR HWUC, *PHWUC;
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#define BIT(x) (1 << (x))
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//
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// VC range supported by the aic5900
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//
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#define MAX_VCS 1024
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#define MIN_VCS 0
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//
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// NIC Cell clock rate.
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//
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//
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//
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#define CELL_CLOCK_25MHZ (25000000)
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#define CELL_CLOCK_16MHZ (16000000)
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//
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// PCI id's
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//
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#define ADAPTEC_PCI_VENDOR_ID 0x9004
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#define AIC5900_PCI_DEVICE_ID 0x5900
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//
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// Adaptec ATM adapter models supported.
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//
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#define ANA_5910 5
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#define ANA_5930 7
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#define ANA_5940 8
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#define ANA_INVALID (UINT)-1
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//
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//
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//
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//
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#define ATM_ADDRESS_LENGTH 6
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#define PCI_DEVICE_SPECIFIC_OFFSET 0x40
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typedef union _PCI_DEVICE_CONFIG
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{
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struct
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{
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UCHAR SoftwareReset:1;
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UCHAR EnableInterrupt:1;
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UCHAR TargetSwapBytes:1;
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UCHAR MasterSwapBytes:1;
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UCHAR EnableIncrement:1;
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UCHAR SoftwareInterrupt:1;
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UCHAR TestDMA:1;
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UCHAR Reserved:1;
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};
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UCHAR reg;
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}
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PCI_DEVICE_CONFIG,
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*PPCI_DEVICE_CONFIG;
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typedef union _PCI_DEVICE_STATUS
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{
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struct
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{
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UCHAR VoltageSense:1;
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UCHAR IllegalByteEnable:1;
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UCHAR IllegalWrite:1;
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UCHAR IllegalOverlap:1;
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UCHAR IllegalDescriptor:1;
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UCHAR Reserved:3;
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};
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UCHAR reg;
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}
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PCI_DEVICE_STATUS,
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*PPCI_DEVICE_STATUS;
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typedef union _PCI_DEVICE_INTERRUPT_STATUS
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{
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struct
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{
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UCHAR DprInt:1;
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UCHAR reserved:2;
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UCHAR StaInt:1;
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UCHAR RtaInt:1;
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UCHAR RmaInt:1;
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UCHAR SseInt:1;
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UCHAR DpeInt:1;
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};
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UCHAR reg;
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}
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PCI_DEVICE_INTERRUPT_STATUS,
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*PPCI_DEVICE_INTERRUPT_STATUS;
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typedef union _PCI_DEVICE_ENABLE_PCI_INTERRUPT
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{
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struct
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{
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UCHAR EnableDprInt:1;
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UCHAR reserved:2;
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UCHAR EnableStaInt:1;
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UCHAR EnableRtaInt:1;
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UCHAR EnableRmaInt:1;
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UCHAR EnableSseInt:1;
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UCHAR EnableDpeInt:1;
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};
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UCHAR reg;
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}
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PCI_DEVICE_ENABLE_PCI_INTERRUPT,
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*PPCI_DEVICE_ENABLE_PCI_INTERRUPT;
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typedef union _PCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS
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{
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struct
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{
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UCHAR GPIOREG0:1;
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UCHAR GPIOREG1:1;
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UCHAR GPIOREG2:1;
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UCHAR GPIOREG3:1;
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UCHAR reserved:4;
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};
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UCHAR reg;
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}
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PCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS,
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*PPCI_DEVICE_GENERAL_PURPOSE_IO_REGISTERS;
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typedef union _PCI_DEVICE_GENERAL_PURPOSE_IOCTL
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{
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struct
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{
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UCHAR GPIOCTL0:1;
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UCHAR GPIOCTL1:1;
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UCHAR GPIOCTL2:1;
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UCHAR GPIOCTL3:1;
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UCHAR reserved:4;
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};
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UCHAR reg;
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}
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PCI_DEVICE_GENERAL_PURPOSE_IOCTL,
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*PPCI_DEVICE_GENERAL_PURPOSE_IOCTL;
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typedef union _PCI_DEVICE_DMA_CONTROL
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{
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struct
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{
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UCHAR StopOnPerr:1;
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UCHAR DualAddressCycleEnable:1;
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UCHAR CacheThresholdEnable:1;
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UCHAR MemoryReadCmdEnable:1;
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UCHAR Reserved:4;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DMA_CONTROL,
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*PPCI_DEVICE_DMA_CONTROL;
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typedef union _PCI_DEVICE_DMA_STATUS
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{
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struct
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{
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UCHAR FifoEmpty:1;
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UCHAR FifoFull:1;
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UCHAR FifoThreshold:1;
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UCHAR HostDmaDone:1;
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UCHAR FifoCacheThreshold:1;
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UCHAR Reserved:3;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DMA_STATUS,
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*PPCI_DEVICE_DMA_STATUS;
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typedef union _PCI_DEVICE_DMA_DIAG
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{
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struct
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{
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UCHAR HostDmaEnable:1;
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UCHAR DataPathDirection:1;
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UCHAR Reserved:6;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DMA_DIAG,
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*PPCI_DEVICE_DMA_DIAG;
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typedef union _PCI_DEVICE_HOST_COUNT
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{
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struct
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{
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ULONG hcLowLow:8;
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ULONG hcLowHigh:8;
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ULONG hcHighLow:8;
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ULONG Reserved:8;
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};
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ULONG reg;
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}
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PCI_DEVICE_HOST_COUNT,
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*PPCI_DEVICE_HOST_COUNT;
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typedef union _PCI_DEVICE_DATA_FIFO_READ_ADDRESS
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{
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struct
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{
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UCHAR MasterFifoPointer:7;
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UCHAR Reserved:1;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DATA_FIFO_READ_ADDRESS,
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*PPCI_DEVICE_DATA_FIFO_READ_ADDRESS;
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typedef union _PCI_DEVICE_DATA_FIFO_WRITE_ADDRESS
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{
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struct
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{
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UCHAR MasterFifoPointer:7;
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UCHAR Reserved:1;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DATA_FIFO_WRITE_ADDRESS,
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*PPCI_DEVICE_DATA_FIFO_WRITE_ADDRESS;
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typedef union _PCI_DEVICE_DATA_FIFO_THRESHOLD
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{
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struct
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{
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UCHAR Reserved0:2;
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UCHAR DFTHRSH:4;
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UCHAR Reserved1:2;
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};
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UCHAR reg;
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}
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PCI_DEVICE_DATA_FIFO_THRESHOLD,
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*PPCI_DEVICE_DATA_FIFO_THRESHOLD;
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typedef union _PCI_DEVICE_LOW_HOST_ADDRESS
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{
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struct
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{
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UCHAR lhaLowLow;
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UCHAR lhaLowHigh;
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UCHAR lhaHighLow;
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UCHAR lhaHighHigh;
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};
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ULONG reg;
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}
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PCI_DEVICE_LOW_HOST_ADDRESS,
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*PPCI_DEVICE_LOW_HOST_ADDRESS;
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typedef union _PCI_DEVICE_HIGH_HOST_ADDRESS
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{
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struct
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{
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ULONG hhaLowLow:8;
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ULONG hhaLowHigh:8;
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ULONG hhaHighLow:8;
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ULONG hhaHighHigh:8;
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};
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ULONG reg;
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}
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PCI_DEVICE_HIGH_HOST_ADDRESS,
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*PPCI_DEVICE_HIGH_HOST_ADDRESS;
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typedef union _PCI_DEVICE_FIFO_DATA_REGISTER
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{
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struct
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{
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ULONG dfrLowLow:8;
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ULONG dfrLowHigh:8;
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ULONG dfrHighLow:8;
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ULONG dfrHighHigh:8;
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};
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ULONG reg;
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}
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PCI_DEVICE_FIFO_DATA_REGISTER,
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*PPCI_DEVICE_FIFO_DATA_REGISTER;
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typedef union _PCI_DEVICE_DATA_ADDRESS
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{
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struct
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{
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ULONG daLowLow:8;
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ULONG daLowHigh:8;
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ULONG daHighLow:8;
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ULONG daHighHigh:8;
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};
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ULONG reg;
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}
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PCI_DEVICE_DATA_ADDRESS,
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*PPCI_DEVICE_DATA_ADDRESS;
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typedef union _PCI_DEVICE_DATA_PORT
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{
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struct
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{
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ULONG dpLowLow:8;
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ULONG dpLowHigh:8;
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ULONG dpHighLow:8;
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ULONG dpHighHigh:8;
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};
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ULONG reg;
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}
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PCI_DEVICE_DATA_PORT,
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*PPCI_DEVICE_DATA_PORT;
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#define PCI_DEVICE_CONFIG_OFFSET 0x40
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#define PCI_DEVICE_STATUS_OFFSET 0x41
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#define PCI_INTERRUPT_STATUS_OFFSET 0x44
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#define PCI_ENABLE_INTERRUPT_OFFSET 0x45
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#define PCI_GENERAL_PURPOSE_IO_PORT_OFFSET 0x46
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#define PCI_GENERAL_PURPOSE_IOCTL_OFFSET 0x47
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#define PCI_DMA_CONTROL_OFFSET 0x4C
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#define PCI_DMA_STATUS_OFFSET 0x4D
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#define PCI_DMA_DIAGNOSTIC_OFFSET 0x4E
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#define PCI_HOST_COUNT0_OFFSET 0x50
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#define PCI_HOST_COUNT1_OFFSET 0x51
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#define PCI_HOST_COUNT2_OFFSET 0x52
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#define PCI_DATA_FIFO_READ_ADDRESS_OFFSET 0x54
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#define PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET 0x55
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#define PCI_DATA_FIFO_THRESHOLD_OFFSET 0x56
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#define PCI_LOW_HOST_ADDRESS0_OFFSET 0x58
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#define PCI_LOW_HOST_ADDRESS1_OFFSET 0x59
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#define PCI_LOW_HOST_ADDRESS2_OFFSET 0x5A
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#define PCI_LOW_HOST_ADDRESS3_OFFSET 0x5B
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#define PCI_HIGH_HOST_ADDRESS0_OFFSET 0x5C
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#define PCI_HIGH_HOST_ADDRESS1_OFFSET 0x5D
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#define PCI_HIGH_HOST_ADDRESS2_OFFSET 0x5E
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#define PCI_HIGH_HOST_ADDRESS3_OFFSET 0x5F
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#define PCI_FIFO_DATA_REGISTER0_OFFSET 0x60
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#define PCI_FIFO_DATA_REGISTER1_OFFSET 0x61
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#define PCI_FIFO_DATA_REGISTER2_OFFSET 0x62
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#define PCI_FIFO_DATA_REGISTER3_OFFSET 0x63
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#define SET_PCI_DEV_CFG(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_CONFIG_OFFSET), (_reg))
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#define GET_PCI_DEV_CFG(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_CONFIG_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_STATUS(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_STATUS_OFFSET), (_reg))
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#define GET_PCI_DEV_STATUS(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DEVICE_STATUS_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_INT_STATUS(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_INTERRUPT_STATUS_OFFSET), (_reg))
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#define GET_PCI_DEV_INT_STATUS(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_INTERRUPT_STATUS_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_ENABLE_INT(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_ENABLE_INTERRUPT_OFFSET), (_reg))
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#define GET_PCI_DEV_ENABLE_INT(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_ENABLE_INTERRUPT_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_GP_IO_REG(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IO_PORT_OFFSET), (_reg))
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#define GET_PCI_DEV_GP_IO_REG(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IO_PORT_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_GP_IOCTL(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IOCTL_OFFSET), (_reg))
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#define GET_PCI_DEV_GP_IOCTL(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_GENERAL_PURPOSE_IOCTL_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DMA_CONTROL(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_CONTROL_OFFSET), (_reg))
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#define GET_PCI_DEV_DMA_CONTROL(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_CONTROL_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DMA_STATUS(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_STATUS_OFFSET), (_reg))
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#define GET_PCI_DEV_DMA_STATUS(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_STATUS_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DMA_DIAG(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_DIAGNOSTIC_OFFSET), (_reg))
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#define GET_PCI_DEV_DMA_DIAG(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DMA_DIAGNOSTIC_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DATA_READ_ADDRESS(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_READ_ADDRESS_OFFSET), (_reg))
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#define GET_PCI_DEV_DATA_READ_ADDRESS(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_READ_ADDRESS_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DATA_WRITE_ADDRESS(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET), (_reg))
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#define GET_PCI_DEV_DATA_WRITE_ADDRESS(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_WRITE_ADDRESS_OFFSET), (PUCHAR)(_reg))
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#define SET_PCI_DEV_DATA_THRESHOLD(_HwInfo, _reg) NdisWriteRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_THRESHOLD_OFFSET), (_reg))
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#define GET_PCI_DEV_DATA_THRESHOLD(_HwInfo, _reg) NdisReadRegisterUchar(((_HwInfo)->PciConfigSpace + PCI_DATA_FIFO_THRESHOLD_OFFSET), (PUCHAR)(_reg))
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//////////////////////////////////////////////////////////////////////////
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//
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// SUNI REGISTER SET
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//
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//////////////////////////////////////////////////////////////////////////
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//
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// SUNI Master Reset and Identify register.
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//
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#define SUNI_MASTER_RESET_IDENTITY 0x00
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#define SET_SUNI_MASTER_RESET_IDEN(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_RESET_IDENTITY), (_value))
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#define GET_SUNI_MASTER_RESET_IDEN(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_RESET_IDENTITY), (_value))
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#define fSUNI_MRI_RESET 0x80
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//
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// RACP Interrupt Enable/Status
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//
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#define SUNI_RACP_INTERRUPT_ENABLE_STATUS 0x144
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#define SET_SUNI_RACP_INT_ENABLE_STATUS(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_RACP_INTERRUPT_ENABLE_STATUS), (_value))
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#define GET_SUNI_RACP_INT_ENABLE_STATUS(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_RACP_INTERRUPT_ENABLE_STATUS), (_value))
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#define fSUNI_RACP_IES_FUDRI 0x01
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#define fSUNI_RACP_IES_FOVRI 0x02
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#define fSUNI_RACP_IES_UHCSI 0x04
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#define fSUNI_RACP_IES_CHCSI 0x08
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#define fSUNI_RACP_IES_OOCDI 0x10
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#define fSUNI_RACP_IES_FIFOE 0x20
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#define fSUNI_RACP_IES_HCSE 0x40
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#define fSUNI_RACP_IES_OOCDE 0x80
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//
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// Master Test
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//
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#define SUNI_MASTER_TEST 0x200
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#define SET_SUNI_MASTER_TEST(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_TEST), (_value))
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#define GET_SUNI_MASTER_TEST(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + SUNI_MASTER_TEST), (_value))
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//////////////////////////////////////////////////////////////////////////
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//
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// IBM 25Mbp TC chipset
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//
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//////////////////////////////////////////////////////////////////////////
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#define IBM_TC_STATUS 0x00
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#define SET_IBM_TC_STATUS(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_STATUS), (_value))
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#define GET_IBM_TC_STATUS(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_STATUS), (_value))
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#define IBM_TC_MODE 0x00
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#define SET_IBM_TC_MODE(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_MODE), (_value))
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#define GET_IBM_TC_MODE(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_MODE), (_value))
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#define IBM_TC_FLUSH_RECEIVE_FIFO 0x00
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#define SET_IBM_TC_FLUSH_RECEIVE_FIFO(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_FLUSH_RECEIVE_FIFO), (_value))
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#define GET_IBM_TC_FLUSH_RECEIVE_FIFO(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_FLUSH_RECEIVE_FIFO), (_value))
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#define IBM_TC_SOFTWARE_RESET 0x00
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#define SET_IBM_TC_SOFTWARE_RESET(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_SOFTWARE_RESET), (_value))
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#define GET_IBM_TC_SOFTWARE_RESET(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_SOFTWARE_RESET), (_value))
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#define IBM_TC_MASK 0x00
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#define SET_IBM_TC_MASK(_HwInfo, _value) NdisWriteRegisterUchar(((_HwInfo)->Phy + IBM_TC_MASK), (_value))
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#define GET_IBM_TC_MASK(_HwInfo, _value) NdisReadRegisterUchar(((_HwInfo)->Phy + IBM_TC_MASK), (_value))
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#endif // __HW_H
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