454 lines
16 KiB
C
454 lines
16 KiB
C
/*+
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* file: mii.h
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*
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* Copyright (C) 1992-1995 by
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* Digital Equipment Corporation, Maynard, Massachusetts.
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* All rights reserved.
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*
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* This software is furnished under a license and may be used and copied
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* only in accordance of the terms of such license and with the
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* inclusion of the above copyright notice. This software or any other
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* copies thereof may not be provided or otherwise made available to any
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* other person. No title to and ownership of the software is hereby
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* transferred.
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*
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* The information in this software is subject to change without notice
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* and should not be construed as a commitment by digital equipment
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* corporation.
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*
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* Digital assumes no responsibility for the use or reliability of its
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* software on equipment which is not supplied by digital.
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*
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*
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* Abstract: This file contains the definition of the MII protocol
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* This file is part of the DEC's DC21X4 Ethernet Controller
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* driver
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*
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* Author: Claudio Hazan
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*
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* Revision History:
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*
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* 20-Nov-95 ch Initial version
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* 20-Dec-95 phk Modified
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*
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-*/
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#define PHY_ADDR_ALIGN 23 // shift
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#define REG_ADDR_ALIGN 18 // shift
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#define MII_MDO_BIT_POSITION 17
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#define MII_MDI_BIT_POSITION 19
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#define MII_DELAY 1 // uS
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#define MII_WRITE ((ULONG) (0x00002000))
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#define MII_CLK ((ULONG) (0x00010000))
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#define MII_MDO_MASK ((ULONG) (0x00020000))
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#define MII_MDI_MASK ((ULONG) (0x00080000))
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#define PRE ((ULONG) (0xFFFFFFFF))
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#define MII_READ_FRAME ((ULONG) (0x60000000))
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#define MII_WRITE_FRAME ((ULONG) (0x50020000))
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#define TEST_PATTERN 0xAA5500FF
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#define CSR_READ 0x4000
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#define SEL_SROM 0x0800
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#define RESET_DELAY 10000
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// MII related bits in CSR9
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#define MII_READ ((ULONG) 0x00044000)
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#define MII_WRITE_TS ((ULONG) 0x00042000)
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#define MII_DATA_1 ((ULONG) 0x00020000) // MDO = 1
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#define MII_DATA_0 ((ULONG) 0x00000000) // MDO = 0
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#define MII_10BITS_TO_MDO_SHIFT 5 // number of left shifts needed to
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// put MSB of MII_PhyAddr packed
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// with MII_RegNumber in the MDO
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// bit position at CSR9
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#define MII_16BITS_TO_MDO_SHIFT 2 // number of left shifts needed to
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// put MSB of MII write data in
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// the MDO bit position at CSR9
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#define MII_READ_DATA_MASK MII_MDI_MASK // MDI bit mask
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#define MAX_PHYADD 32
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//PHY Types
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#define PHY_NUMBER 0 // No Multiple PHYs support yet
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#define MAX_PHY_TABLE (PHY_NUMBER+1)
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#define MAX_GPR_SEQUENCE 5
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#define MAX_RESET_SEQUENCE 5
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#define NO_SELECTED_PHY 0x00FF
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#define MiiPhyCtrlReset ((USHORT) 0x8000)
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#define MiiPhyCtrlLoopBack ((USHORT) 0x4000)
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#define MiiPhyCtrlSpeed100 ((USHORT) 0x2000)
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#define MiiPhyCtrlEnableNway ((USHORT) 0x1000)
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#define MiiPhyCtrlPowerDown ((USHORT) 0x0800)
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#define MiiPhyCtrlIsolate ((USHORT) 0x0400)
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#define MiiPhyCtrlRestartNway ((USHORT) 0x0200)
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#define MiiPhyCtrlDuplexMode ((USHORT) 0x0100)
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#define MiiPhyCtrlCollisionTest ((USHORT) 0x0080)
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#define MiiPhyCtrlReservedBitsMask ((USHORT) 0x007F)
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#define MiiPhyCtrlForce10 ((USHORT) 0xCEFF)
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#define MiiPhy100BaseT4 ((USHORT) 0x8000)
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#define MiiPhy100BaseTxFD ((USHORT) 0x4000)
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#define MiiPhy100BaseTx ((USHORT) 0x2000)
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#define MiiPhy10BaseTFD ((USHORT) 0x1000)
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#define MiiPhy10BaseT ((USHORT) 0x0800)
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#define MiiPhyStatReservedBitsMask ((USHORT) 0x07C0)
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#define MiiPhyNwayComplete ((USHORT) 0x0020)
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#define MiiPhyRemoteFault ((USHORT) 0x0010)
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#define MiiPhyNwayCapable ((USHORT) 0x0008)
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#define MiiPhyLinkStatus ((USHORT) 0x0004)
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#define MiiPhyJabberDetect ((USHORT) 0x0002)
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#define MiiPhyExtendedCapabilities ((USHORT) 0x0001)
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#define MiiPhyMediaCapabilitiesMask (MiiPhy100BaseT4 | \
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MiiPhy100BaseTxFD | \
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MiiPhy100BaseTx | \
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MiiPhy10BaseTFD | \
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MiiPhy10BaseT)
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#define MiiPhyCapabilitiesMask (MiiPhyMediaCapabilitiesMask | \
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MiiPhyNwayCapable)
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// Vendors' PHY IDs
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//National
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#define DP83840_0 ((ULONG) 0x20005C00)
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//Broadcom
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#define BCM5000_0 ((ULONG) 0x03E00000)
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#define MII_BROADCOM_EXTENDED_REG_ADDRESS 16
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#define BROADCOM_EXT_REG_FORCE_FAIL_EN_MASK 0x100
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#define BROADCOM_EXT_REG_SPEED_MASK 0x2
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//Generic
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#define GENERIC_PHY ((ULONG) 0xFFFFFFFF)
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// Useful masks
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#define VENDOR_ID_MASK ((ULONG) 0xFFFFFC00)
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#define VENDOR_ID_RIGHT_JUSTIFY 10
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#define VENDOR_MODEL_MASK ((USHORT) 0x03F0)
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#define VENDOR_MODEL_RIGHT_JUSTIFY 4
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#define VENDOR_Rev_MASK ((USHORT) 0x000F)
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#define MiiPhyNwayNextPageAble ((USHORT) 0x8000)
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#define MiiPhyNwayACK ((USHORT) 0x4000)
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#define MiiPhyNwayRemoteFault ((USHORT) 0x2000)
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#define MiiPhyNwayReservedBitsMask ((USHORT) 0x1C00)
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#define MiiPhyNway100BaseT4 ((USHORT) 0x0200)
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#define MiiPhyNway100BaseTxFD ((USHORT) 0x0100)
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#define MiiPhyNway100BaseTx ((USHORT) 0x0080)
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#define MiiPhyNway10BaseTFD ((USHORT) 0x0040)
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#define MiiPhyNway10BaseT ((USHORT) 0x0020)
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#define MiiPhyNwaySelectorMask ((USHORT) 0x001F)
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// MiiPhyNwayCapabilitiesMask - 0x03E0
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#define MiiPhyNwayCapabilitiesMask (MiiPhyNway100BaseT4 | \
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MiiPhyNway100BaseTxFD | \
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MiiPhyNway100BaseTx | \
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MiiPhyNway10BaseTFD | \
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MiiPhyNway10BaseT)
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#define NWAY_802_3_Selector 1
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#define MiiPhyNwayExpReservedBitsMask ((USHORT) 0xFFE0)
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#define MiiPhyNwayExpMultipleLinkFault ((USHORT) 0x0010)
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#define MiiPhyNwayExpLinkPartnerNextPageAble ((USHORT) 0x0008)
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#define MiiPhyNwayExpNextPageAble ((USHORT) 0x0004)
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#define MiiPhyNwayExpReceivedLinkCodePage ((USHORT) 0x0002)
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#define MiiPhyNwayExpLinkPartnerNwayAble ((USHORT) 0x0001)
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// MII PHY Register's
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#define PhyControlReg 0
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#define PhyStatusReg 1
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#define PhyId_1 2
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#define PhyId_2 3
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#define PhyNwayAdvertisement 4
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#define PhyNwayLinkPartnerAbility 5
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#define PhyNwayExpansion 6
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#define PhyNwayNextPageTransmit 7
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#define PhyReserved 8 // 8-15 are PHY's reserved
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#define PhyVendorSpecific 16 // 16-31 are Vendor's Specific
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#define NatPhyParRegister 25
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#define MAX_PHY_REGS 32
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#define DELAY(_time) NdisStallExecution(_time)
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//National Phy PAR Register
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#define PAR_SPEED_10 ((USHORT)0x0040)
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// MAC connection capabilities
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#define MAC_CONN_UNKNOWN ((USHORT) 0xFFFF)
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//PHY Type Values
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#define PHY_TYPE_UNKNOWN ((UCHAR) 0xFF) // Initializing, true state or type not known
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#define PHY_TYPE_SIA 0 // 10MB/s Manchester
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#define PHY_TYPE_MII 1 // MII PHY
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//PHY Operation Modes
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#define PHY_OM_UNKNOWN ((UCHAR) 0xFF)
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//PHY_OM_AUTOSENSE
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#define PHY_OM_NWAY MiiPhyNwayCapable
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#define PHY_NO_SPECIAL_OM 0
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//Media Attachment Interface Status
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#define MAI_UNKNOWN ((UCHAR) 0xFF)
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#define MAI_Absent 0
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#define MAI_Present 1
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#define MAI_PresentConnected 3
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// MAU list
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#define MAU_UNKNOWN 0
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#define MAU_10BaseT MiiPhy10BaseT
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#define MAU_10BaseTFD MiiPhy10BaseTFD
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//MAU_BNC
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//MAU_AUI
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#define MAU_100BaseT4 MiiPhy100BaseT4
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#define MAU_100BaseTX MiiPhy100BaseTx
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#define MAU_100BaseFX MiiPhy100BaseTx
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#define MAU_100BaseTXFD MiiPhy100BaseTxFD
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#define MAU_100BaseFXFD MiiPhy100BaseTxFD
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//MAU_10BaseFX
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#define NWAY_10BaseT MiiPhyNway10BaseT
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#define NWAY_100BaseT4 MiiPhyNway100BaseT4
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#define NWAY_100BaseTX MiiPhyNway100BaseTx
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#define NWAY_10BaseTFD MiiPhyNway10BaseTFD
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#define NWAY_100BaseTXFD MiiPhyNway100BaseTxFD
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// define Media status
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#define MEDIA_STATE_UNKNOWN 0x00FF
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#define MEDIA_STATE_UNDEFINED 0x00FE
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#define MEDIA_READ_REGISTER_FAILED 0x00FD
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#define MEDIA_LINK_FAIL 0x0000
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#define MEDIA_LINK_PASS 0x0001
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#define MEDIA_LINK_PASS_WITH_PF 0x0002
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#define MEDIA_STATUS_MASK 0x00FF
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// define NWAY Availability & status
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#define NWAY_UNKNOWN 0xFF00 //PHY is still initializing
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#define NWAY_NOT_SUPPORTED 0x0000 //No NWAY in this Phy
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#define NWAY_SUPPORTED 0x0100 //NWAY supported
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#define NWAY_DISABLED 0x0200 //NWAY present but disabled
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#define NWAY_CONFIGURING 0x0300 //NWAY still configuring
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#define NWAY_COMPLETE 0x0400 //NWAY negotiation is done
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#define NWAY_STATUS_MASK 0xFF00
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typedef enum _MII_STATUS {
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MiiGenAdminReset,
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MiiGenAdminOperational,
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MiiGenAdminStandBy,
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MiiGenAdminPowerDown,
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MiiGenAdminForce10,
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MiiGenAdminForce10Fd,
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MiiGenAdminRelease10
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} MII_STATUS, *PMII_STATUS;
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typedef USHORT CAPABILITY, *PCAPABILITY;
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typedef struct _PHY_EXT_ROUTINES_ENTRIES {
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BOOLEAN (*PhyInit)(PDC21X4_ADAPTER,PMII_PHY_INFO);
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void (*PhyGetCapabilities)(PMII_PHY_INFO,PCAPABILITY);
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BOOLEAN (*PhySetConnectionType)(PDC21X4_ADAPTER,PMII_PHY_INFO,USHORT,USHORT);
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BOOLEAN (*PhyGetConnectionType)(PDC21X4_ADAPTER,PMII_PHY_INFO,PUSHORT);
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BOOLEAN (*PhyGetConnectionStatus)(PDC21X4_ADAPTER,PMII_PHY_INFO,PUSHORT);
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void (*PhyAdminStatus)(PDC21X4_ADAPTER,PMII_PHY_INFO,PMII_STATUS);
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void (*PhyAdminControl)(PDC21X4_ADAPTER,PMII_PHY_INFO,PMII_STATUS);
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}PHY_EXT_ROUTINES_ENTRIES;
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typedef struct _PHY_INT_ROUTINES_ENTRIES {
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BOOLEAN (*PhyReadRegister)(PDC21X4_ADAPTER,PMII_PHY_INFO,USHORT,PUSHORT);
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BOOLEAN (*PhyWriteRegister)(PDC21X4_ADAPTER,PMII_PHY_INFO,USHORT,PUSHORT);
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void (*PhyNwayGetLocalAbility)(PDC21X4_ADAPTER,PMII_PHY_INFO,PCAPABILITY);
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void (*PhyNwaySetLocalAbility)(PDC21X4_ADAPTER,PMII_PHY_INFO,USHORT);
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void (*PhyNwayGetPartnerAbility)(PDC21X4_ADAPTER,PMII_PHY_INFO,PCAPABILITY);
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}PHY_INT_ROUTINES_ENTRIES;
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typedef struct _MII_PHY_INFO {
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BOOLEAN StructValid;
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USHORT PhyAddress;
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ULONG PhyId;
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USHORT PhyCapabilities;
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USHORT PhyMediaAdvertisement;
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USHORT PhyRegs[MAX_PHY_REGS];
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USHORT PreviousControl;
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PHY_EXT_ROUTINES_ENTRIES PhyExtRoutines;
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PHY_INT_ROUTINES_ENTRIES PhyIntRoutines;
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} MII_PHY_INFO, *PMII_PHY_INFO;
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typedef struct _MII_GEN_INFO {
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USHORT NumOfPhys;
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USHORT PhysCapabilities;
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USHORT SelectedPhy; // 0 means that all phys are isolated
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PMII_PHY_INFO Phys[MAX_PHY_TABLE];
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} MII_GEN_INFO, *PMII_GEN_INFO;
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//Data Structure holding PHY's registers mask
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static const USHORT PhyRegsReservedBitsMasks[] = {
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MiiPhyCtrlReservedBitsMask, // Control reg reserved bits mask
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MiiPhyStatReservedBitsMask, // Status reg reserved bits PhyID reserved bits mask
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0, // PhyID reserved bits mask
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0, // PhyID reserved bits mask
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MiiPhyNwayReservedBitsMask, // Nway Local ability reserved bits mask
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MiiPhyNwayReservedBitsMask, // Nway Partner ability reserved bits mask
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MiiPhyNwayExpReservedBitsMask, // Nway Expansion
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0,0,0,0,0,0,0,0,0,0,0,0,0, // Other regs
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0,0,0,0,0,0,0,0,0,0,0,0 // Other regs
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};
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static const UINT AdminControlConversionTable[] = {
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MiiPhyCtrlReset, // Reset
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0x0, // Operational
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MiiPhyCtrlIsolate, // StandBy / Isolate
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MiiPhyCtrlPowerDown, // Powerdown
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0x0, // Force10
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MiiPhyCtrlDuplexMode, // Force10Fd
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0x0 // Release10
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};
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static const USHORT MediaBitTable[] = {
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0x0000, // TP
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0x0000, // BNC
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0x0000, // AUI
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0x0000, // 100BaseTx/SymScr
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0x0000, // TP-FD
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0x0000, // 100BaseTx-FD/SymScr-FD
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0x0000, // 100BaseT4
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0x0000, // 100BaseFx
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0x0000, // 100BaseFx-FD
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0x0800, // MediaMiiTP
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0x1000, // MediaMiiTpFD
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0x0000, // MediaMiiBNC
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0x0000, // MediaMiiAUI
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0x2000, // MediaMii100BaseTX
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0x4000, // MediaMii100BaseTxFD
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0x8000, // MediaMii100BaseT4
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0x0000, // MediaMii100BaseFX
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0x0000 // MediaMii100BaseFxFD
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};
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static const USHORT ConvertMediaTypeToMiiType[] = {
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0x0009, // TP -> MII TP
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0x000B, // BNC -> MII BNC
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0x000C, // AUI -> MII AUI
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0x000D, // 100BaseTx -> MII 100BaseTx
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0x020A, // TP-FD -> MII TP-FD
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0x020E, // 100BaseTx-FD -> MII 100BaseTxFD
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0x000F, // 100BaseT4 -> MII 100BaseT4
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0x0010, // 100BaseFx -> MII 100BaseFx
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0x0211 // 100BaseFx-FD -> MII 100BaseFxFD
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};
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static const USHORT MediaToCommandConversionTable[] = {
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0x0000, // TP
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0x0000, // BNC
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0x0000, // AUI
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0x2000, // 100BaseTx/SymScr
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0x0100, // TP-FD
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0x2100, // 100BaseTx-FD/SymScr-FD
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0x2000, // 100BaseT4
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0x2000, // 100BaseFx
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0x2100, // 100BaseFx-FD
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0x0000, // MediaMiiTP
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0x0100, // MediaMiiTpFD
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0x0000, // MediaMiiBNC
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0x0000, // MediaMiiAUI
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0x2000, // MediaMii100BaseTX
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0x2100, // MediaMii100BaseTxFD
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0x2000, // MediaMii100BaseT4
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0x2000, // MediaMii100BaseFX
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0x2100 // MediaMii100BaseFxFD
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};
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static const USHORT MediaToNwayConversionTable[] = {
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0x0020, // TP
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0x0000, // BNC
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0x0000, // AUI
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0x0080, // 100BaseTx/SymScr
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0x0040, // TP-FD
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0x0100, // 100BaseTx-FD/SymScr-FD
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0x0200, // 100BaseT4
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0x0080, // 100BaseFx
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0x0100, // 100BaseFx-FD
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0x0020, // MediaMiiTP
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0x0040, // MediaMiiTpFD
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0x0000, // MediaMiiBNC
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0x0000, // MediaMiiAUI
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0x0080, // MediaMii100BaseTX
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0x0100, // MediaMii100BaseTxFD
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0x0200, // MediaMii100BaseT4
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0x0080, // MediaMii100BaseFX
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0x0100 // MediaMii100BaseFxFD
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};
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static const USHORT MediaToStatusConversionTable[] = {
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0x0800, // TP
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0x0000, // BNC
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0x0000, // AUI
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0x2000, // 100BaseTx/SymScr
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0x1000, // TP-FD
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0x4000, // 100BaseTx-FD/SymScr-FD
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0x8000, // 100BaseT4
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0x2000, // 100BaseFx
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0x4000, // 100BaseFx-FD
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0x0800, // MediaMiiTP
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0x1000, // MediaMiiTpFD
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0x0000, // MediaMiiBNC
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0x0000, // MediaMiiAUI
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0x2000, // MediaMii100BaseTX
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0x4000, // MediaMii100BaseTxFD
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0x8000, // MediaMii100BaseT4
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0x2000, // MediaMii100BaseFX
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0x4000 // MediaMii100BaseFxFD
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};
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