668 lines
16 KiB
C
668 lines
16 KiB
C
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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tokhrd.h
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Abstract:
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The hardware-related definitions for the IBMTOK drivers.
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Author:
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Anthony V. Ercolano (tonye) creation-date 19-Jun-1990
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Adam Barr (adamba) 18-Feb-1991
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Environment:
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Architecturally, there is an assumption in this driver that we are
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on a little endian machine.
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Notes:
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optional-notes
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Revision History:
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Sean Selitrennikoff - 9/??/91
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Added/Changed definitions to allow for Microchannel cards too.
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--*/
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#ifndef _IBMTOKHARDWARE_
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#define _IBMTOKHARDWARE_
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//
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// Types of adapters this driver can work with
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//
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#define IBM_TOKEN_RING_PCMCIA 1
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//
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// Initialization Status Flag Bit Settings
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//
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#define RINGSPEEDLISTEN 0x40
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//
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// Token-Ring Controller Configuration Register control bits
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// Used by IBM_TOKEN_RING_16_4_CREDIT_CARD_ADAPTER
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//
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// #define DEFAULT_MMIO 0xD4000
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// #define DEFAULT_RAM 0xD6
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#define DEFAULT_MMIO 0xC2000
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#define DEFAULT_RAM 0xD0
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#define SHARED_RAM_64K 0xC
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#define SHARED_RAM_32K 0x8
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#define SHARED_RAM_16K 0x4
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#define SHARED_RAM_8K 0x0
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#define RING_SPEED_16_MPS 0x2
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#define RING_SPEED_4_MPS 0x0
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#define PRIMARY 0x0
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#define ALTERNATE 0x1
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#define DEFAULT_NIBBLE_2 0x6
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#define NIBBLE_0 0x00
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#define NIBBLE_1 0x10
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#define NIBBLE_2 0x20
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#define NIBBLE_3 0x30
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#define RELEASE_TR_CONTROLLER 0x40
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//
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// IBM Token Ring Adapter IDs
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//
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#define IBMTOK1_ADAPTER_ID 0xE000
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#define IBMTOK2_ADAPTER_ID 0xE001
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//
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// Start of I/O ports based on which adapter it is.
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//
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#define PRIMARY_ADAPTER_OFFSET 0xa20
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#define ALTERNATE_ADAPTER_OFFSET 0xa24
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//
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// Offsets from above of the actual ports used.
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//
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#define SWITCH_READ_1 0x000
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#define RESET_LATCH 0x001
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#define SWITCH_READ_2 0x002
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#define RESET_RELEASE 0x002
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#define INTERRUPT_RELEASE_ISA_ONLY 0x003
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//
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// Registers in the MMIO. These are in the Attachment
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// Control Area, which starts at offset 0x1e00 of the ACA.
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//
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#define RRR_LOW 0x1e00
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#define RRR_HIGH 0x1e01
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#define WRBR_LOW 0x1e02
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#define WRBR_HIGH 0x1e03
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#define ISRP_LOW 0x1e08
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#define ISRP_LOW_RESET 0x1e28
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#define ISRP_LOW_SET 0x1e48
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#define ISRP_HIGH 0x1e09
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#define ISRP_HIGH_RESET 0x1e29
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#define ISRA_LOW 0x1e0a
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#define ISRA_HIGH 0x1e0b
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#define ISRA_HIGH_SET 0x1e4b
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#define TCR_LOW 0x1e0c
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#define TCR_HIGH 0x1e0d
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#define TVR_LOW 0x1e0e
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#define TVR_HIGH 0x1e0f
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#define SRPR_LOW 0x1e18
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#define SRPR_HIGH 0x1e19
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//
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// These are registers in the AIP (aka the ID PROM),
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// which starts at offset 0x1f00 of the ACA.
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//
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#define CHANNEL_IDENTIFIER 0x1f30
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#define TOTAL_ADAPTER_RAM 0x1fa6
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#define SHARED_RAM_PAGING 0x1fa8
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#define MAX_4_MBPS_DHB 0x1faa
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#define MAX_16_MBPS_DHB 0x1fac
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//
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// Bits in the ISRA Low (even) register.
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//
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#define ISRA_LOW_TIMER_INTERRUPT 0x40
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#define ISRA_LOW_INTERRUPT_MASK 0x01
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//
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// Bits in the ISRA High (odd) register.
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//
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#define ISRA_HIGH_COMMAND_IN_SRB 0x20
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#define ISRA_HIGH_RESPONSE_IN_ASB 0x10
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#define ISRA_HIGH_SRB_FREE_REQUEST 0x08
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#define ISRA_HIGH_ASB_FREE_REQUEST 0x04
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#define ISRA_HIGH_ARB_FREE 0x02
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#define ISRA_HIGH_SSB_FREE 0x01
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//
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// Bits in the ISRP Low (even) register.
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//
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#define ISRP_LOW_NO_CHANNEL_CHECK 0x80
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#define ISRP_LOW_INTERRUPT_ENABLE 0x40
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//
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// Bits in the ISRP High (odd) register.
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//
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#define ISRP_HIGH_ADAPTER_CHECK 0x40
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#define ISRP_HIGH_SRB_RESPONSE 0x20
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#define ISRP_HIGH_ASB_FREE 0x10
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#define ISRP_HIGH_ARB_COMMAND 0x08
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#define ISRP_HIGH_SSB_RESPONSE 0x04
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//
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// Bits in the TCR Low (even) register.
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//
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#define TCR_LOW_INTERRUPT_MASK 0x80
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#define TCR_LOW_RELOAD_TIMER 0x40
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#define TCR_LOW_COUNTER_ENABLE 0x20
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#define WRITE_ADAPTER_REGISTER(a, r, v) \
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NdisWriteRegisterUchar((PUCHAR)((a)->MmioRegion + (r)), (UCHAR)(v))
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#define READ_ADAPTER_REGISTER(a, r, v) \
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NdisReadRegisterUchar((PUCHAR)(a)->MmioRegion + (r), (PUCHAR)(v))
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#define WRITE_ADAPTER_PORT(a, p, v) \
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NdisWritePortUchar((a)->NdisAdapterHandle, (ULONG)((a)->IbmtokPortAddress + (p)), (UCHAR)(v))
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#define READ_ADAPTER_PORT(a, p, v) \
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NdisReadPortUchar((a)->NdisAdapterHandle, (ULONG)(a)->IbmtokPortAddress + (p), (PUCHAR)(v))
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//
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// An IBMSHORT is a short that is in IBM byte ordering,
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// with the high and low bytes reversed.
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//
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typedef USHORT IBMSHORT;
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//
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// NOTE: These are dangerous because s appears twice in them.
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//
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#define READ_IBMSHORT(s) (USHORT)((((PUCHAR)&s)[0] << 8) + ((PUCHAR)&s)[1])
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#define WRITE_IBMSHORT(s, val) {\
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USHORT _tmp; \
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_tmp = (USHORT)((((val) >> 8) & 0xff) | (((val) & 0xff) << 8)); \
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NdisWriteRegisterUshort((PUSHORT)&s, _tmp); \
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}
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#define USHORT_TO_IBMSHORT(val) (IBMSHORT)((((val) >> 8) & 0xff) | \
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(((val) & 0xff) << 8))
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#define IBMSHORT_TO_USHORT(val) (USHORT)((((val) >> 8) & 0xff) | \
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(((val) & 0xff) << 8))
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//
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// An SRAM_PTR is a pointer into the Shared RAM on the adapter.
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// It uses the IBM byte ordering.
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//
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typedef IBMSHORT SRAM_PTR;
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#define NULL_SRAM_PTR ((SRAM_PTR)0x0000)
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#define SRAM_PTR_TO_PVOID(a, p) \
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((PVOID)((a)->SharedRam + IBMSHORT_TO_USHORT(p)))
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#define SHARED_RAM_ADDRESS(a, p) \
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((PVOID)((a)->SharedRam + ((ULONG)(p))))
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//
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// Macros to deal with the frame status field.
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//
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#define GET_FRAME_STATUS_HIGH_AC(Fs) ((UCHAR)(((Fs) & 0xc0) >> 6))
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#define GET_FRAME_STATUS_LOW_AC(Fs) ((UCHAR)(((Fs) & 0x0c) >> 2))
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#define AC_NOT_RECOGNIZED 0x00
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#define AC_INVALID 0x01
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#define AC_NOT_COPIED 0x10
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#define AC_COPIED 0x11
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//
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// Some adapters have to have the upper section of the
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// Shared RAM zeroed out after initialization.
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//
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#define SHARED_RAM_ZERO_OFFSET ((PVOID)0xfe00)
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#define SHARED_RAM_ZERO_LENGTH 0x0200
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//
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// The highest command correlator used by the adapter
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// transmit logic.
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//
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#define MAX_COMMAND_CORRELATOR 128
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//
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// This macro is used to set up the SRPR depending on
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// the given address (should only be called if it is
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// known that the adapter supports Shared RAM Paging!!).
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//
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#define SETUP_SRPR(Adapter, Address) \
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WRITE_ADAPTER_REGISTER((Adapter), SRPR_LOW, ((ULONG)(Address) >> 14))
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//
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// This macro retrieves the part of an address that
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// is used once SETUP_SRPR has been called.
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//
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#define SHARED_RAM_LOW_BITS(Address) \
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((ULONG)(Address) & 0x3fff)
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//
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// This macro determines if an address will fit on a
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// single Shared RAM page. It makes sure that the beginning
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// and end of the sequence have the same high two bits.
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//
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#define SINGLE_SHARED_RAM_PAGE(Address, Length) \
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(((ULONG)(Address) & 0xc000) == (((ULONG)(Address)+(Length)-1) & 0xc000))
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//
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// Various structures which are read after the adapter
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// is reset.
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//
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typedef struct _ADAPTER_ADDRESS {
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UCHAR NodeAddress[6];
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UCHAR GroupAddress[4];
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UCHAR FunctionalAddress[4];
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} ADAPTER_ADDRESS, * PADAPTER_ADDRESS;
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typedef struct _ADAPTER_PARAMETERS {
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UCHAR PhysicalAddress[4];
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UCHAR NaunNodeAddress[6];
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UCHAR NaunPhysicalAddress[4];
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UCHAR LastPoolAddress[6];
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UCHAR Reserved1[2];
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IBMSHORT TransmitAccessPriority;
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IBMSHORT SourceClassAuthorization;
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IBMSHORT LastAttentionCode;
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UCHAR LastSourceAddress[6];
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IBMSHORT LastBeaconType;
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IBMSHORT LastMajorVector;
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IBMSHORT RingStatus;
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IBMSHORT SoftErrorTimer;
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IBMSHORT FrontEndError;
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IBMSHORT LocalRingNumber;
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IBMSHORT MonitorErrorCode;
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IBMSHORT BeaconTransmitType;
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IBMSHORT BeaconReceiveType;
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IBMSHORT FrameCorrelator;
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UCHAR BeaconNaun[6];
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UCHAR Reserved2[4];
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UCHAR BeaconPhysicalAddress[4];
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} ADAPTER_PARAMETERS, * PADAPTER_PARAMETERS;
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typedef struct _SRB_BRING_UP_RESULT {
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UCHAR Command;
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UCHAR InitStatus;
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UCHAR Reserved1[4];
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IBMSHORT ReturnCode;
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SRAM_PTR EncodedAddressPointer;
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SRAM_PTR LevelAddressPointer;
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SRAM_PTR AdapterAddressPointer; // points to ADAPTER_ADDRESS
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SRAM_PTR ParameterAddressPointer; // points to ADAPTER_PARAMETERS
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SRAM_PTR MacBufferPointer;
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} SRB_BRING_UP_RESULT, * PSRB_BRING_UP_RESULT;
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//
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// Structure of the System Request Block as defined
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// for various commands.
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//
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typedef struct _SRB_GENERIC {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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} SRB_GENERIC, * PSRB_GENERIC;
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//
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// Values for the SRB Command field.
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//
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#define SRB_CMD_CLOSE_ADAPTER 0x04
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#define SRB_CMD_INTERRUPT 0x00
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#define SRB_CMD_MODIFY_OPEN_PARMS 0x01
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#define SRB_CMD_OPEN_ADAPTER 0x03
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#define SRB_CMD_CLOSE_ADAPTER 0x04
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#define SRB_CMD_READ_LOG 0x08
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#define SRB_CMD_RESTORE_OPEN_PARMS 0x02
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#define SRB_CMD_SET_FUNCTIONAL_ADDRESS 0x07
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#define SRB_CMD_SET_GROUP_ADDRESS 0x06
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#define SRB_CMD_TRANSMIT_DIR_FRAME 0x0a
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#define SRB_CMD_DLC_STATISTICS 0x1e
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typedef struct _SRB_OPEN_ADAPTER {
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UCHAR Command;
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UCHAR Reserved1[7];
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IBMSHORT OpenOptions;
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UCHAR NodeAddress[6];
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UCHAR GroupAddress[4];
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UCHAR FunctionalAddress[4];
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IBMSHORT ReceiveBufferNum;
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IBMSHORT ReceiveBufferLen;
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IBMSHORT TransmitBufferLen;
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UCHAR TransmitBufferNum;
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UCHAR Reserved2[1];
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UCHAR DlcValues[10];
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UCHAR ProductId[18];
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} SRB_OPEN_ADAPTER, * PSRB_OPEN_ADAPTER;
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typedef struct _SRB_CLOSE_ADAPTER {
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UCHAR Command;
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UCHAR Reserved1;
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UCHAR ReturnCode;
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} SRB_CLOSE_ADAPTER, * PSRB_CLOSE_ADAPTER;
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//
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// Bit values for the OpenOptions field (these are
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// reversed to be in IBMSHORT format).
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//
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#define OPEN_LOOPBACK 0x0080
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#define OPEN_DISABLE_HARD_ERROR 0x0040
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#define OPEN_DISABLE_SOFT_ERROR 0x0020
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#define OPEN_PASS_ADAPTER_MAC 0x0010
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#define OPEN_PASS_ATTENTION_MAC 0x0008
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#define OPEN_CONTENDER 0x0001
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#define OPEN_PASS_BEACON_MAC 0x8000
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#define OPEN_MODIFIED_TOKEN_RELEASE 0x1000
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#define OPEN_REMOTE_PROGRAM_LOAD 0x2000
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typedef struct _SRB_OPEN_RESPONSE {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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UCHAR Reserved2[3];
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IBMSHORT ErrorCode;
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SRAM_PTR AsbPointer;
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SRAM_PTR SrbPointer;
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SRAM_PTR ArbPointer;
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SRAM_PTR SsbPointer;
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} SRB_OPEN_RESPONSE, * PSRB_OPEN_RESPONSE;
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typedef struct _SRB_TRANSMIT_DIR_FRAME {
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UCHAR Command;
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UCHAR CommandCorrelator;
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UCHAR ReturnCode;
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UCHAR Reserved1[1];
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IBMSHORT StationId;
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} SRB_TRANSMIT_DIR_FRAME, * PSRB_TRANSMIT_DIR_FRAME;
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typedef struct _SRB_SET_FUNCT_ADDRESS {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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UCHAR Reserved2[3];
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//
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// Making this a TR_FUNCTIONAL_ADDRESS would cause
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// the compiler to insert two bytes for alignment.
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//
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UCHAR FunctionalAddress[4];
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} SRB_SET_FUNCT_ADDRESS, * PSRB_SET_FUNCT_ADDRESS;
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typedef struct _SRB_SET_GROUP_ADDRESS {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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UCHAR Reserved2[3];
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//
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// Making this a TR_FUNCTIONAL_ADDRESS would cause
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// the compiler to insert two bytes for alignment.
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//
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UCHAR GroupAddress[4];
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} SRB_SET_GROUP_ADDRESS, * PSRB_SET_GROUP_ADDRESS;
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typedef struct _SRB_INTERRUPT {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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} SRB_INTERRUPT, * PSRB_INTERRUPT;
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typedef struct _SRB_READ_LOG {
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UCHAR Command;
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UCHAR Reserved1[1];
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UCHAR ReturnCode;
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UCHAR Reserved2[3];
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UCHAR LineErrors;
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UCHAR InternalErrors;
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UCHAR BurstErrors;
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UCHAR AcErrors;
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UCHAR AbortDelimeters;
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UCHAR Reserved3[1];
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UCHAR LostFrames;
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UCHAR ReceiveCongestionCount;
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UCHAR FrameCopiedErrors;
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UCHAR FrequencyErrors;
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UCHAR TokenErrors;
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UCHAR Reserved4[3];
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} SRB_READ_LOG, * PSRB_READ_LOG;
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typedef struct _SRB_DLC_STATS{
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UCHAR Command;
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UCHAR Reserved1;
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UCHAR ReturnCode;
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UCHAR Reserved2;
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IBMSHORT StationId;
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IBMSHORT CountersOffset;
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IBMSHORT HeaderAddr;
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UCHAR ResetOption;
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}SRB_DLC_STATS, *PSRB_DLC_STATS;
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typedef struct _DLC_COUNTERS{
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IBMSHORT TransmitCount;
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IBMSHORT ReceiveCount;
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UCHAR TransmitErrors;
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UCHAR ReceiveErrors;
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IBMSHORT T1Expires;
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UCHAR ReceivedCommand;
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UCHAR SentCommand;
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UCHAR PrimaryState;
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UCHAR SecondaryState;
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UCHAR SendState;
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UCHAR ReceiveState;
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UCHAR LastReceivedNr;
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}DLC_COUNTERS, *PDLC_COUNTERS;
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//
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// Structure of the Adapter Request Block as defined
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// for various commands.
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//
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typedef struct _ARB_GENERIC {
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UCHAR Command;
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} ARB_GENERIC, * PARB_GENERIC;
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//
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// Values for the ARB Command field.
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//
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#define ARB_CMD_DLC_STATUS 0x83
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#define ARB_CMD_RECEIVED_DATA 0x81
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#define ARB_CMD_RING_STATUS_CHANGE 0x84
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#define ARB_CMD_TRANSMIT_DATA_REQUEST 0x82
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typedef struct _ARB_RING_STATUS_CHANGE {
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UCHAR Command;
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UCHAR Reserved1[5];
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IBMSHORT NetworkStatus;
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} ARB_RING_STATUS_CHANGE, * PARB_RING_STATUS_CHANGE;
|
|
|
|
|
|
typedef struct _ARB_DLC_STATUS {
|
|
UCHAR Command;
|
|
UCHAR Reserved1[3];
|
|
IBMSHORT StationId;
|
|
IBMSHORT Status;
|
|
UCHAR FrmrData[5];
|
|
UCHAR AccessPriority;
|
|
UCHAR RemoteAddress[6];
|
|
UCHAR RemoteRsapValue;
|
|
} ARB_DLC_STATUS, * PARB_DLC_STATUS;
|
|
|
|
|
|
typedef struct _ARB_TRANSMIT_DATA_REQUEST {
|
|
UCHAR Command;
|
|
UCHAR CommandCorrelator;
|
|
UCHAR Reserved1[2];
|
|
IBMSHORT StationId;
|
|
SRAM_PTR DhbPointer;
|
|
} ARB_TRANSMIT_DATA_REQUEST, * PARB_TRANSMIT_DATA_REQUEST;
|
|
|
|
|
|
typedef struct _ARB_RECEIVED_DATA {
|
|
UCHAR Command;
|
|
UCHAR Reserved1[3];
|
|
IBMSHORT StationId;
|
|
SRAM_PTR ReceiveBuffer; // points to a RECEIVE_BUFFER
|
|
UCHAR LanHeaderLength;
|
|
UCHAR DlcHeaderLength;
|
|
IBMSHORT FrameLength;
|
|
UCHAR MessageType;
|
|
} ARB_RECEIVED_DATA, * PARB_RECEIVED_DATA;
|
|
|
|
|
|
typedef struct _RECEIVE_BUFFER {
|
|
//
|
|
// Leave out the first two reserved bytes.
|
|
//
|
|
SRAM_PTR NextBuffer;
|
|
UCHAR Reserved2[1];
|
|
UCHAR ReceiveFs;
|
|
IBMSHORT BufferLength;
|
|
UCHAR FrameData[1];
|
|
} RECEIVE_BUFFER, * PRECEIVE_BUFFER;
|
|
|
|
|
|
|
|
|
|
//
|
|
// Structure of the Adapter Status Block as defined
|
|
// for various commands.
|
|
//
|
|
|
|
typedef struct _ASB_GENERIC {
|
|
UCHAR Command;
|
|
UCHAR Reserved1[1];
|
|
UCHAR ReturnCode;
|
|
} ASB_GENERIC, * PASB_GENERIC;
|
|
|
|
|
|
//
|
|
// The ASB Command field takes the same values as the
|
|
// ARB Command field.
|
|
//
|
|
|
|
typedef struct _ASB_TRANSMIT_DATA_STATUS {
|
|
UCHAR Command;
|
|
UCHAR CommandCorrelator;
|
|
UCHAR ReturnCode;
|
|
UCHAR Reserved1[1];
|
|
IBMSHORT StationId;
|
|
IBMSHORT FrameLength;
|
|
UCHAR Reserved2[2];
|
|
} ASB_TRANSMIT_DATA_STATUS, * PASB_TRANSMIT_DATA_STATUS;
|
|
|
|
|
|
typedef struct _ASB_RECEIVED_DATA_STATUS {
|
|
UCHAR Command;
|
|
UCHAR Reserved1[1];
|
|
UCHAR ReturnCode;
|
|
UCHAR Reserved2[1];
|
|
IBMSHORT StationId;
|
|
SRAM_PTR ReceiveBuffer;
|
|
} ASB_RECEIVED_DATA_STATUS, * PASB_RECEIVED_DATA_STATUS;
|
|
|
|
|
|
|
|
|
|
//
|
|
// Structure of the System Status Block as defined
|
|
// for various commands.
|
|
//
|
|
|
|
typedef struct _SSB_GENERIC {
|
|
UCHAR Command;
|
|
} SSB_GENERIC, * PSSB_GENERIC;
|
|
|
|
|
|
//
|
|
// The SSB Command field takes the same values as the
|
|
// SRB Command field.
|
|
//
|
|
|
|
typedef struct _SSB_TRANSMIT_COMPLETE {
|
|
UCHAR Command;
|
|
UCHAR CommandCorrelator;
|
|
UCHAR ReturnCode;
|
|
UCHAR Reserved1[1];
|
|
IBMSHORT StationId;
|
|
UCHAR ErrorFrameStatus;
|
|
} SSB_TRANSMIT_COMPLETE, * PSSB_TRANSMIT_COMPLETE;
|
|
|
|
|
|
|
|
#endif // _IBMTOKHARDWARE_
|