607 lines
25 KiB
C
607 lines
25 KiB
C
/***********************************************************************/
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/***********************************************************************/
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/* */
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/* File Name: TMSSTRCT.H */
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/* */
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/* Program Name: NetFlex NDIS 3.0 Driver */
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/* */
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/* Companion Files: None */
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/* */
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/* Function: This module contains all the data strcuture defini- */
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/* tions that are specific to the TMS380 software */
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/* interface specification. The data structures */
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/* defined are as follows: */
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/* */
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/* - TMS380 Adapter Command Definitions */
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/* - TMS380 SIF Register Offset Definitions */
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/* - Adapter Interrupt Register Bit Definition */
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/* - Adapter Configuration Register Bit Definition */
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/* - TMS380 Adapter Command Definitions */
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/* - System Command Block (SCB) */
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/* - System Status Block (SSB) */
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/* - Adapter Initialization Parameter Block */
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/* - Adapter Open Parameter Block */
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/* - Adapter Transmit Parameter List */
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/* - Transmit CSTAT Bit Definitions */
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/* - Transmit Status Bit Definitions */
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/* - Adapter Receive Parameter List */
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/* - Receive CSTAT Bit Definitions */
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/* - Receive Status Bit Definitions */
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/* - Read Error Log Buffer Definition */
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/* */
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/* (c) Compaq Computer Corporation, 1992,1993,1994 */
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/* */
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/* This file is licensed by Compaq Computer Corporation to Microsoft */
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/* Corporation pursuant to the letter of August 20, 1992 from */
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/* Gary Stimac to Mark Baber. */
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/* */
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/* History: */
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/* */
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/* 05/24/94 Robert Van Cleve - Reworked from NDIS 3.0 Driver */
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/* */
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/***********************************************************************/
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/***********************************************************************/
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#define NET_ADDR_SIZE 6
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#define NET_GROUP_SIZE 4
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#define HDR_SIZE 14
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/*
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* Structure Name: TMS380 Adapter Command Definitions
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*
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* Description: The TMS380 Adapter Commands Definitions define the
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* reversed byte ordering of the TMS380 adapter command
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* word values.
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*/
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#define TMS_RESET 0x0000 /* Reset Adapter (doesn't exist) */
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#define TMS_CMDREJECT 0x0200 /* Command Reject */
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#define TMS_OPEN 0x0300 /* Open Adapter */
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#define TMS_TRANSMIT 0x0400 /* Transmit Frame */
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#define TMS_XMITHALT 0x0500 /* Transmit Halt */
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#define TMS_RECEIVE 0x0600 /* Receive */
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#define TMS_CLOSE 0x0700 /* Close Adapter */
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#define TMS_SETGROUP 0x0800 /* Set Group Address */
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#define TMS_SETFUNCT 0x0900 /* Set Functional Address */
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#define TMS_READLOG 0x0a00 /* Read Error Log */
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#define TMS_READADP 0x0b00 /* Read Adapter Buffer */
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#define TMS_MODIFYOPEN 0x0d00 /* Modify Open Parameters */
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#define TMS_MULTICAST 0x1200 /* Set/Clr Multicast Address */
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#define TMS_DUMMYCMD 0x1111 /* Dummy SCB */
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/*
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* Structure Name: TMS380 SIF Register Offset Definitions
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*
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* Description: The TMS380 Register Offset Definitions describe the
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* offsets to and number of TMS380 SIF registers.
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*/
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#define NUMREGS 4
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#define SIF_DATA_OFF 0x0 /* SIF data register */
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#define SIF_DINC_OFF 0x2 /* SIF data autoincrment reg */
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#define SIF_ADDR_OFF 0x4 /* SIF address register */
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#define SIF_INT_OFF 0x6 /* SIF interrupt register */
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#define SIF_ACTL_OFF 0x8 /* SIF ACTL register */
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#define SIF_ACTL_EXT_OFF 0xc /* SIF Address Extended reg */
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#define PORT0 0 /* Regular single port adapter */
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#define PORT1 1 /* Port 1 of dual port adapter */
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#define PORT2 2 /* Port 2 of dual port adapter */
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/*
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* Structure Name: Adapter Control Register Bit Definitions
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*
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* Description: The Adapter Control Register Bit Definitions define
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* functions of the individual bits in the Adapter Con-
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* trol register of the EAGLE chip. Bit combinations are
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* also defined here.
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*/
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#define ACTL_TEST0 0x8000 /* Test0, set - 4mbps, clr - 16 */
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#define ACTL_TEST1 0x4000 /* Test1, set - TR, clr - Eth */
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#define ACTL_SWHLDA 0x0800 /* Software Hold Acknowledge */
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#define ACTL_SWDDIR 0x0400 /* Current SDDIR signal level */
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#define ACTL_SWHRQ 0x0200 /* Software Hold Request */
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#define ACTL_PSDMALEN 0x0100 /* Psuedo System DMA Length */
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#define ACTL_ARESET 0x0080 /* Adapter Reset */
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#define ACTL_CPHALT 0x0040 /* Comm Processor Halt */
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#define ACTL_BOOT 0x0020 /* Bootstrapped CP Code */
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#define ACTL_ROM 0x0010 /* Reserved */
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#define ACTL_SINTEN 0x0008 /* System Interrupt Enable */
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#define ACTL_PEN 0x0004 /* Adapter Parity Enable */
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#define ACTL_NSELOUT0 0x0002 /* Net Select, set - 4, clr -16 */
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#define ACTL_NSELOUT1 0x0001 /* Net Select,set - tr, clr -eth*/
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#define ACTL_TESTPINS ACTL_TEST1 + ACTL_TEST0
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#define ACTL_HARD_RESET 0xEE /* Force Hard Reset */
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#define SIF_SOFT_RESET 0xff00 /* Soft Reset */
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/*
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* Structure Name: Adapter Interrupt Register Bit Definitions
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*
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* Description: The Adapter Interrupt Register Bit Definitions define
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* functions of the individual bits in the System Inter-
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* rupt register of the TMS380 chipset. Bit combinations
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* are also defined here.
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*/
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#define SIFINT_ADPINT 0x8000 /* Adapter Interrupt */
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#define SIFINT_RESET 0x4000 /* Reset request */
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#define SIFINT_SSBCLR 0x2000 /* SSB Clear */
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#define SIFINT_EXECUTE 0x1000 /* Execute Command */
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#define SIFINT_SCBREQ 0x0800 /* SCB Clear request */
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#define SIFINT_RCVCON 0x0400 /* Receive Continue */
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#define SIFINT_RCVVLD 0x0200 /* Receive Valid */
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#define SIFINT_XMTVLD 0x0100 /* Transmit Valid */
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#define SIFINT_SYSINT 0x0080 /* System Interrupt */
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#define SIFINT_CMD (SIFINT_ADPINT | SIFINT_EXECUTE | SIFINT_SYSINT)
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#define SIFINT_SSBCLEAR (SIFINT_ADPINT | SIFINT_SSBCLR)
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#define SIFINT_SCBREQST (SIFINT_ADPINT | SIFINT_SCBREQ | SIFINT_SYSINT)
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#define SIFINT_RCVVALID (SIFINT_ADPINT | SIFINT_RCVVLD | SIFINT_SYSINT)
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#define SIFINT_XMTVALID (SIFINT_ADPINT | SIFINT_XMTVLD | SIFINT_SYSINT)
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#define SIFINT_RCVCONT (SIFINT_ADPINT | SIFINT_RCVCON | SIFINT_SYSINT)
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#define INT_ADPCHECK 0x0000 /* Adapter Check Interrupt */
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#define INT_RINGSTAT 0x0004 /* Ring Status Interrupt */
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#define INT_SCBCLEAR 0x0006 /* SCB Clear Interrupt */
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#define INT_COMMAND 0x0008 /* Command Interrupt */
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#define INT_TRANSMIT 0x000c /* Transmit Interrupt */
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#define INT_RECEIVE 0x000a /* Receive Interrupt */
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#define INT_CODES 0x000f /* Mask for interrupt codes */
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/*
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* Structure Name: Address Register INIT Block Location Definition
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*
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* Description: The Address Register INIT Block Loaction Definition defines
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* the value that must be placed into the SIF address reg
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* when the TMS380 is being initialized.
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*/
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#define ADDR_INIT 0x0a00 /* Start at address 0x0a00 */
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/*
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* Structure Name: System Command Block (SCB) Structure Definition
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*
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* Description: The System Command Block Structure Definition defines
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* the structure of the TMS380 based SCB block.
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*/
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typedef struct SCB_Block
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{
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USHORT SCB_Dummy; /* Force SCB.Ptr to word boundry */
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USHORT SCB_Cmd; /* SCB Command field */
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ULONG SCB_Ptr; /* SCB Pointer field */
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} SCB, *PSCB;
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#define SIZE_SCB sizeof(SCB)
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/*
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* Structure Name: System Status Block (SSB) Structure Definition
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*
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* Description: The System Status Block Structure Definition defines
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* the structure of the TMS380 based SSB block. Also in-
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* cluded are the SSB status field bit definitions.
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*/
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typedef struct SSB_Block
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{
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USHORT SSB_Cmd; /* SSB Command field */
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USHORT SSB_Status; /* SSB Status field */
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ULONG SSB_Ptr; /* SSB Pointer field */
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} SSB, *PSSB;
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#define SIZE_SSB sizeof(SSB)
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#define SSB_GOOD 0x0080 /* SSB Command successful status */
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#define SSB_OPENERR 0x0002 /* Open Error Completion */
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/*
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* Structure Name: Adapter Initialization Parameter Block Definition
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*
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* Description: The Adapter Initialization Parameter Block Definition
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* defines the structure of the TMS380 based initiali-
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* zation block.
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*/
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typedef struct INIT_Block
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{
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USHORT INIT_Options; /* Initialization Options */
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UCHAR INIT_Vectors[6]; /* Interrupt vector codes */
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USHORT INIT_Rburst; /* Receive DMA burst size */
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USHORT INIT_Xburst; /* Transmit DMA burst size */
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USHORT INIT_DMARetry; /* DMA retry counts */
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} INIT, *PINIT;
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#define SIZE_INIT sizeof(INIT)
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//
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// Structure Name: Open Adapter Parameter Block Structure Definition
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//
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// Description: The Open Adapter Parameter Block Structure Definition
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// defines the structure of the TMS380 based parameter
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// block passed to the adapter on an Open Adapter request.
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// All parameter defaults listed here are already byte
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// swapped for DMA into the adapter. Open options are
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// also defined here.
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//
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typedef struct OPEN_Block
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{
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USHORT OPEN_Options; /* Open options */
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UCHAR OPEN_NodeAddr[NET_ADDR_SIZE]; /* Adapter node addr */
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UCHAR OPEN_GroupAddr[NET_GROUP_SIZE]; /* Adapter grp addr */
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UCHAR OPEN_FunctAddr[NET_GROUP_SIZE]; /* Adapter fnc addr */
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USHORT OPEN_RLSize; /* Receive list size */
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USHORT OPEN_XLSize; /* Transmit list size */
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USHORT OPEN_BufSize; /* Adapter buffer size (1K) */
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USHORT OPEN_RAMStart; /* Adapter RAM start addr */
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USHORT OPEN_RAMEnd; /* Adapter RAM end address */
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UCHAR OPEN_Xbufmin; /* Adapter xmit min buf cnt */
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UCHAR OPEN_Xbufmax; /* Adapter xmit max buf cnt */
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UCHAR *OPEN_ProdIdPtr; /* Product ID pointer */
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UCHAR OPEN_ProdID[18]; /* Product ID */
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} OPEN, *POPEN;
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#define SIZE_OPEN sizeof(OPEN)
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#define OOPTS_WRAP 0x8000 /* Open Wrap Mode BOTH */
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#define OOPTS_DHARD 0x4000 /* Disable Hard Errors TR */
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#define OOPTS_DSOFT 0x2000 /* Disable Soft Errors TR */
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#define OOPTS_PADPM 0x1000 /* Pass Adapter MAC Frames TR */
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#define OOPTS_PATTM 0x0800 /* Pass Attention MAC Frames TR */
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#define OOPTS_PADR 0x0400 /* Pad Routing Field TR */
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#define OOPTS_FHOLD 0x0200 /* Frame Hold BOTH */
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#define OOPTS_CONT 0x0100 /* Contender TR */
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#define OOPTS_SHFR 0x0100 /* Pad Short Frames ETH */
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#define OOPTS_PBCNM 0x0080 /* Pass Beacon MAC Frames TR */
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#define OOPTS_REQ 0x0040 /* Required bit. ETH */
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#define OOPTS_FULLDUP 0x0020 /* Full duplex enable ETH */
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#define OOPTS_ETR 0x0010 /* Early Token Release TR */
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#define OOPTS_CMAC 0x0004 /* Copy All MAC Frames TR */
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#define OOPTS_CNMAC 0x0002 /* Copy All Non-MAC Frames BOTH */
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#define OOPTS_FONLY 0x0001 /* Pass First Buffer Only */
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#define OOPTS_TR_CFG 0xff87 /* Token ring configurable bits */
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#define OOPTS_ETH_CFG 0x8263 /* Ethernet configurable bits */
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//
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// Structure Name: Transmit List Data Pointer Structure Definition
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//
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// Description: The Transmit List Data Pointer Structure Definition
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// defines the structure of the data pointers contained
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// in the TMS380 based Transmit Parameter List.
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//
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typedef struct _XMIT_DATA
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{
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USHORT DataCount;
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USHORT DataHi;
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USHORT DataLo;
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} XMIT_DATA, *PXMIT_DATA;
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#define DATA_NOT_LAST 0x0080 /* "Not last" mask for len field*/
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#define DATA_LAST 0xff7f /* "Last" mask for len field */
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//
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// Structure Name: Transmit List Structure Definition
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//
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// Description: The Transmit List Structure Definition defines the
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// structure of the TMS380 based Transmit Parameter List.
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// Also included are the definitions of the TRNDD parti-
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// cular fields that have been added to the end of the
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// list structure to allow easy management of the trans-
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// mit process.
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//
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#define MAX_LISTS_PER_XMIT 1
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#define NUM_BUFS_PER_LIST 6 // MAC Can Handle max of 9 fragments
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#define MAX_BUFS_PER_XMIT (MAX_LISTS_PER_XMIT * NUM_BUFS_PER_LIST)
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#define SIZE_XMIT_DATA (NUM_BUFS_PER_LIST * 6) // 3 words per
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#define SIZE_XMIT_LIST (SIZE_XMIT_DATA + 8) // data + fwrdptr + size + count
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//
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// Definition of the buffer structures we need for recieve lists,
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// and our own transmit buffers.
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//
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typedef struct _BUFFER_DESCRIPTOR {
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NDIS_PHYSICAL_ADDRESS PhysicalBuffer;
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PVOID VirtualBuffer;
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PNDIS_BUFFER FlushBuffer;
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struct _BUFFER_DESCRIPTOR *Next; // NULL implies no more entries in the list.
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UINT BufferSize; // bytes available in the buffer
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UINT DataLength; // actual bytes placed into buffer.
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} BUFFER_DESCRIPTOR, *PBUFFER_DESCRIPTOR;
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typedef struct XMIT_List
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{
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// Hardware List Fields
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//
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ULONG XMIT_FwdPtr; // Motorola pointer to next list
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USHORT XMIT_CSTAT; // Command/Status field
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SHORT XMIT_Fsize; // Frame size
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XMIT_DATA XMIT_Data[MAX_BUFS_PER_XMIT]; // Data
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struct XMIT_List *XMIT_Next; // Intel pointer to next list
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//
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// Our extra List Fields...
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//
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ULONG XMIT_MyMoto; // My motorola address
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#ifndef COPALL
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ULONG XMIT_MapReg; // Index to mapping register
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PNDIS_PACKET XMIT_Packet; //
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#endif
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NDIS_PHYSICAL_ADDRESS XMIT_Phys; // Physical Pointer to this XMIT
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ULONG XMIT_Timeout; // > 0 if checking for timeout
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#ifdef XMIT_INTS
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ULONG XMIT_Number; // index of this list
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#endif
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PBUFFER_DESCRIPTOR XMIT_OurBufferPtr; // which buffer we used...
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} XMIT, *PXMIT;
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#define SIZE_XMIT sizeof(XMIT) /* Size of transmit list */
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// Structure Name: Transmit List CSTAT Bit Definitions
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//
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// Description: The Transmit List CSTAT Bit Definitions defines the
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// meaning of the bits in the CSTAT field of the transmit
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// list.
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//
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#define XCSTAT_VALID 0x0080 /* Transmit Valid */
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#define XCSTAT_COMPLETE 0x0040 /* Transmit Frame Complete */
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#define XCSTAT_SOF 0x0020 /* Transmit Start of Frame */
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#define XCSTAT_EOF 0x0010 /* Transmit End of Frame */
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#define XCSTAT_FINT 0x0008 /* Transmit Frame Interrupt */
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#define XCSTAT_ERROR 0x0004 /* Transmit Error */
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#define XCSTAT_GOODFS 0x8800 /* Good Transmit FS btye */
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#define XCSTAT_LSOF 0x00a8 /* Transmit Start of Frame */
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#define XCSTAT_GO_INT 0x00b8 /* Transmit VALID/SOF/EOF/FINT */
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#define XCSTAT_GO 0x00b0 /* Transmit VALID/SOF/EOF */
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//
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// Structure Name: Transmit SSB Status Codes Definitions
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//
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// Description: The Transmit SSB Status Codes Definitions defines the
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// meaning of the bits in the Status field of the trans-
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// mit completion SSB.
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//
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#define XSTAT_CMDCMPLT 0x0080 /* Command Complete */
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#define XSTAT_FRMCMPLT 0x0040 /* Frame Complete */
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#define XSTAT_LERROR 0x0020 /* List Error */
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#define XSTAT_FRAME_SIZE_ERROR 0x8000
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#define XSTAT_XMIT_THRESHOLD 0x4000
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#define XSTAT_ODD_ADDRESS 0x2000
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#define XSTAT_FRAME_ERROR 0x1000
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#define XSTAT_ACCESS_PRIORITY_ERR 0x0800
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#define XSTAT_UNENABLE_MAC_FRAME 0x0400
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#define XSTAT_ILLEGAL_FRAME_FORMAT 0x0200
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//
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// Structure Name: Receive List Structure Definition
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//
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// Description: The Receive List Structure Definition defines the
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// structure of the TMS380 based Receive Parameter List.
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// Also included are the definitions of the TRNDD parti-
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// cular fields that have been added to the end of the
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// list structure to allow easy management of the receive
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// process.
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//
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typedef struct RCV_List
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{
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// Physical Hardware List Fields
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//
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ULONG RCV_FwdPtr; /* Motorola pointer to next list*/
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USHORT RCV_CSTAT; /* Command/Status field */
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SHORT RCV_Fsize; /* Frame size */
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USHORT RCV_Dsize; /* Receive list data size */
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USHORT RCV_DptrHi; /* Receive list date pointer hi word*/
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USHORT RCV_DptrLo; /* Receive list data pointer lo word*/
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//
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// Our Extra Receive List Fields
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//
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struct RCV_List *RCV_Next; // Intel pointer to next list
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#ifdef ODD_POINTER
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struct RCV_List *RCV_Prev; // Intel pointer to previous list
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#endif
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ULONG RCV_Number; // index
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ULONG RCV_MyMoto; // Motorola Physical Address
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ULONG RCV_HeaderLen; // Len of the rcvd packet's hdr
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NDIS_PHYSICAL_ADDRESS RCV_Phys; // Physical Pointer to this RCV
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PVOID RCV_Buf; // pointer to our recieve buffer
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NDIS_PHYSICAL_ADDRESS RCV_BufPhys; // Physical Pointer to our Frame Buffer
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PNDIS_BUFFER RCV_FlushBuffer; // Points to an NDIS buffer which describes thisbuffer
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} RCV, *PRCV;
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#define SIZE_RCV sizeof(RCV) // Size of receive list
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//
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// Structure Name: Receive List CSTAT Bit Definitions
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//
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// Description: The Receive List CSTAT Bit Definitions defines the
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// meaning of the bits in the CSTAT field of the receive
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// list.
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//
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#define RCSTAT_VALID 0x0080 /* Receive Valid */
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#define RCSTAT_COMPLETE 0x0040 /* Receive Frame Complete */
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#define RCSTAT_SOF 0x0020 /* Receive Start of Frame */
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#define RCSTAT_EOF 0x0010 /* Receive End of Frame */
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#define RCSTAT_FINT 0x0008 /* Receive Frame Interrupt */
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#define RCSTAT_GO_INT 0x0088 /* Receive Valid and frame int */
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#define RCSTAT_GO 0x0080 /* Receive Valid and frame int */
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//
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// Receive_Status Field Defines
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//
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#define RSTAT_FRAME_COMPLETE 0x0080 /* Frame Complete */
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#define RSTAT_RX_SUSPENDED 0x0040 /* Receive Suspended */
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//
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// Structure Name: Token-Ring Frame Format
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//
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// Description: The Token-Ring Frame Format structure defines the
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// fields of a valid Token-Ring frame.
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//
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typedef struct TR_Format
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{
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|
UCHAR FF_Ac; /* AC Field */
|
|
UCHAR FF_Fc; /* FC Field */
|
|
UCHAR FF_Dest[6]; /* Destination Address */
|
|
UCHAR FF_Src[6]; /* Source Address */
|
|
} TRF, *PTRF;
|
|
|
|
//
|
|
// Structure Name: Source Routing Format
|
|
//
|
|
// Description: The Source Routing Format structure defines the fields
|
|
// of Source Routing information contained within a frame
|
|
//
|
|
typedef struct routing_control
|
|
{
|
|
UCHAR rc_L:5, /* Length of RI including rc */
|
|
rc_B:3; /* Broadcast Bits */
|
|
UCHAR rc_r:3, /* Reserved */
|
|
rc_LF:4, /* Largest Frame */
|
|
rc_D:1; /* Direction bits */
|
|
} ROUTING_CONTROL, *PROUTING_CONTROL;
|
|
|
|
|
|
//
|
|
// Structure Name: Ethernet Frame Format
|
|
//
|
|
// Description: The Ethernet Frame Format structure defines the
|
|
// fields of a valid Ethernet frame.
|
|
//
|
|
typedef struct Eth_Format
|
|
{
|
|
UCHAR FF_Dest[6]; /* Destination Address */
|
|
UCHAR FF_Src[6]; /* Source Address */
|
|
} ETHF, *PETHF;
|
|
|
|
|
|
//
|
|
// MAC Header Size. This is the same header size for both network types.
|
|
//
|
|
#define NETFLEX_MACHEADER_SIZE 14
|
|
|
|
|
|
//
|
|
// Structure Name: Read Error Log Buffer Structure Definition
|
|
// (Token Ring Only)
|
|
//
|
|
// Description: The Read Error Log Buffer Structure Definition defines
|
|
// the structure of the TMS380 based Read Error Log.
|
|
//
|
|
typedef struct REL_Block
|
|
{
|
|
UCHAR REL_LineError;
|
|
UCHAR REL_Rsvd1;
|
|
UCHAR REL_BurstError;
|
|
UCHAR REL_ARIFCIError;
|
|
UCHAR REL_Rsvd2;
|
|
UCHAR REL_Rsvd3;
|
|
UCHAR REL_LostError;
|
|
UCHAR REL_Congestion;
|
|
UCHAR REL_CopiedError;
|
|
UCHAR REL_Rsvd4;
|
|
UCHAR REL_TokenError;
|
|
UCHAR REL_Rsvd5;
|
|
UCHAR REL_DMABUSError;
|
|
UCHAR REL_DMAPARError;
|
|
} REL, *PREL;
|
|
|
|
#define SIZE_REL sizeof(REL)
|
|
|
|
//
|
|
// Structure Name: Read Statistics Log Buffer Structure Definition
|
|
// (Ethernet Only)
|
|
//
|
|
// Description: The Read Statistics Log Buffer Structure Definition defines
|
|
// the structure of the TMS380 based Read Statistics Log.
|
|
//
|
|
typedef struct RSL_Block
|
|
{
|
|
USHORT RSL_ReceviedOK;
|
|
USHORT RSL_Rsvd1;
|
|
USHORT RSL_FrameCheckSeq;
|
|
USHORT RSL_AlignmentErr;
|
|
USHORT RSL_DeferredXmit;
|
|
USHORT RSL_Excessive;
|
|
USHORT RSL_LateCollision;
|
|
USHORT RSL_CarrierErr;
|
|
USHORT RSL_XmitdOK;
|
|
USHORT RSL_1_Collision;
|
|
USHORT RSL_2_Collision;
|
|
USHORT RSL_3_Collision;
|
|
USHORT RSL_4_Collision;
|
|
USHORT RSL_5_Collision;
|
|
USHORT RSL_6_Collision;
|
|
USHORT RSL_7_Collision;
|
|
USHORT RSL_8_Collision;
|
|
USHORT RSL_9_Collision;
|
|
USHORT RSL_10_Collision;
|
|
USHORT RSL_11_Collision;
|
|
USHORT RSL_12_Collision;
|
|
USHORT RSL_13_Collision;
|
|
USHORT RSL_14_Collision;
|
|
USHORT RSL_15_Collision;
|
|
} RSL, *PRSL;
|
|
|
|
#define SIZE_RSL sizeof(RSL)
|
|
|
|
|
|
|
|
struct read_adapter_buf
|
|
{
|
|
SHORT count;
|
|
SHORT addr;
|
|
UCHAR data[100];
|
|
};
|
|
|
|
|
|
typedef struct multi_block
|
|
{
|
|
USHORT MB_Option;
|
|
USHORT MB_Addr_Hi;
|
|
USHORT MB_Addr_Med;
|
|
USHORT MB_Addr_Lo;
|
|
} MULTI_BLOCK, *PMULTI_BLOCK;
|
|
|
|
#define MPB_DELETE_ADDRESS 0x0000
|
|
#define MPB_ADD_ADDRESS 0x0100
|
|
#define MPB_CLEAR_ALL 0x0200
|
|
#define MPB_SET_ALL 0x0300
|
|
|
|
|
|
#define RING_STATUS_OVERFLOW 0x8000
|
|
#define RING_STATUS_SINGLESTATION 0x4000
|
|
#define RING_STATUS_RINGRECOVERY 0x2000
|
|
#define RING_STATUS_SIGNAL_LOSS 0x0080
|
|
#define RING_STATUS_HARD_ERROR 0x0040
|
|
#define RING_STATUS_SOFT_ERROR 0x0020
|
|
#define RING_STATUS_XMIT_BEACON 0x0010
|
|
#define RING_STATUS_LOBE_WIRE_FAULT 0x0008
|
|
#define RING_STATUS_AUTO_REMOVE_1 0x0004
|
|
#define RING_STATUS_REMOVE_RECEIVED 0x0001
|
|
|
|
|