552 lines
13 KiB
ArmAsm
552 lines
13 KiB
ArmAsm
//
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//
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// Copyright (c) 1993 IBM Corporation
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//
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// Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// PXL2.S
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//
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// Abstract:
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//
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// This module implements the routines to size & enable the L2 cache
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// on an Eagle based system.
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//
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// Author:
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//
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// Steve Johns (sjohns@pets.sps.mot.com)
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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// 11-Aug-94 saj Added Eagle L2 cache support for Big Bend.
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// 23-Nov-94 saj Added input parameter specifying write-back or write-thru
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// 01-Dec-94 saj Removed all hardware workarounds
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// Enable L2 Parity error checking (Eagle register 0xC4)
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// 08-Mar-95 saj Added input parameter EagleAC
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// 21-Aug-95 v-matth Steve's sizing functionality is walking on the
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// page file database if we have 128Mb of RAM. I'm
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// going to change it to save off main memory before
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// we do our writes to main memory, then restore those
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// values before we exit.
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// 01-Sep-95 saj Check if L2 is already enabled. If so, just exit.
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// Otherwise, size L2 and exit with L2 disabled. Don't read
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// DBATs, since can't be read reliably on 603e.
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//
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#include "kxppc.h"
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#include "halppc.h"
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.extern HalpIoControlBase
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.set HID0, 1008
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//
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// Eagle register A8 fields:
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//
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.set CF_WRITE_THRU, 0x0001 // Write-through
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.set CF_WRITE_BACK, 0x0002 // Write-back
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.set CF_L2_MP, 0x0003 // Bits 1..0 (LE bit order)
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//
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// Eagle register AC fields:
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//
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.set L2_EN, 0x40000000
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.set L2_UPDATE_EN, 0x80000000
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.set CF_FLUSH_L2, 0x10000000
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.set CF_INV_MODE, 0x00001000
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//
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// L2 cache sizes:
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//
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.set CF_L2_SIZE, 0x0030 // Bits 5..4 (LE bit order)
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.set L2_1M, 0x0020
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.set L2_512K, 0x0010
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.set L2_256K, 0x0000
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.set L2_LINE_SIZE, 32
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//
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// Local parameters
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//
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.set CacheSize, r.3 // Return value
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.set Pattern, r.3
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.set Offset, r.5
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.set EagleA8, r.6
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.set EagleAC, r.7
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.set L2off, r.8 // Eagle register A8 for L2 disabled
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.set Restore, r.9
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.set ISA, r.10 // Pointer to ISA I/O space
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.set Virtual, r.11
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.set Pattern0, 0x77777777 // Patterns for L2 cache sizing
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.set Pattern1, 0x11111111
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.set Pattern2, 0x22222222
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.set Pattern3, 0X33333333
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.set Pattern4, 0x44444444
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.set VIRTUAL, 0xFFC00000 // Virtual address for L2 sizing
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.set PHYSICAL, 0x00C00000 // Physical mem. used for L2 sizing
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.set BAT_REG, 1 // BAT register to use for L2 sizing
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//***********************************************************************
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//
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// Synopsis:
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// ULONG HalpSizeL2(VOID)
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//
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// Purpose:
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// Sizes and enables the Eagle L2 cache.
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//
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// Returns:
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// Size of L2 cache or zero if not installed.
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// Valid sizes are 256, 512, and 1024.
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//
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// Global Variables Referenced:
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// HalpIoControlBase
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//
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// NOTE: Interrupts are assumed to be disabled upon entry.
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//***********************************************************************
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LEAF_ENTRY(HalpSizeL2)
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//
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// Lock the I-cache so instruction fetching doesn't impact the L2 cache
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// while we are sizing it. With the I-cache locked, instruction fetches will
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// not bursted in, so the L2 will not respond to those cycles.
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//
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mfspr r.0, HID0
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ori r.0, r.0, 0x2000 // Lock the Icache
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mtspr HID0, r.0
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//
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// Get ptr to Eagle I/O (ISA bus)
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//
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lwz ISA,[toc]HalpIoControlBase(r.toc) // Get base of ISA I/O
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lwz ISA,0(ISA)
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LWI (EagleA8, 0x800000A8) // Processor Interface Configuration 1
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addi EagleAC, EagleA8, 4 // Processor Interface Configuration 2
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//
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// Return if L2 cache is already enabled.
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//
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.0, 0xCFC(ISA)
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andis. r.4, r.0, (L2_EN >> 16) // Test L2_EN
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beq Init_BAT
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stw EagleA8, 0xCF8(ISA)
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sync
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lwz r.4, 0xCFC(ISA)
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andi. r.4, r.4, CF_L2_MP // Test CF_L2_MP
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beq Init_BAT
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andi. r.0, r.0, CF_L2_SIZE // Isolate L2 size field
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cmpi 0,0,r.0, 0x30 // Reserved ?
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li CacheSize, 0
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beq L2_Exit
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li CacheSize, 256
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cmpi 0,0,r.0, L2_256K
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beq L2_Exit
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li CacheSize, 512
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cmpi 0,0,r.0, L2_512K
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beq L2_Exit
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li CacheSize, 1024
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b L2_Exit
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//
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// Initialize a BAT register to map the memory at PHYSICAL to VIRTUAL.
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// The sizing algorithm depends on the block of memory being marked WRITE-THRU.
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//
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Init_BAT:
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LWI (Virtual, VIRTUAL)
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LWI (r.0, PHYSICAL + 0x5A) // WIMG = 1011; PP = 10
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mtdbatl BAT_REG, r.0
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ori r.0, Virtual, 0x003F // BL = 2MB; Vs = Vp = 1
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mtdbatu BAT_REG, r.0
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isync
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//
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// Save the 4 test locations.
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//
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lis Offset, 4 // Offset = 256K
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lwz Pattern,[toc].LRDATA(rtoc) // Pattern <- address of .LRDATA
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lwz r.0, 0 (Virtual)
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stw r.0, 0 (Pattern) // Save Memory[ 0K];
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dcbf r.0, Virtual
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lwzux r.0, Virtual, Offset
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dcbf r.0, Virtual
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stw r0, 4(Pattern) // Save Memory[256K];
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lwzux r.0, Virtual, Offset
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mr r.9, Virtual // r.9 = Virtual + 512K
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dcbf r.0, Virtual
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stw r0, 8(Pattern) // Save Memory[512K];
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lwzux r.0, Virtual, Offset
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dcbf r.0, Virtual
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stw r0,12(Pattern) // Save Memory[768K];
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LWI (Virtual, VIRTUAL)
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//
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// Set the L2 cache to Write-Through
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//
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stw EagleA8, 0xCF8(ISA)
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sync
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lwz L2off, 0xCFC(ISA)
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rlwinm L2off, L2off,0,~CF_L2_MP
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ori r.0, L2off, CF_WRITE_THRU
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stw r.0, 0xCFC(ISA)
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sync
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//
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// Enable the L2 cache for 1 MB
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//
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.0, 0xCFC(ISA)
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rlwinm r.0, r.0, 0, ~CF_L2_SIZE
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ori r.0, r.0, L2_1M
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oris r.0, r.0, ((L2_EN+L2_UPDATE_EN) >> 16)
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stw r.0, 0xCFC(ISA)
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sync
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sync
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//
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// Load the 4 test locations into the L2 cache.
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//
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lwzx r.0, r.9, Offset // 768 KB
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lwz r.0, 0(r.9) // 512 KB
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lwzx r.0, Virtual, Offset // 256 KB
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lwz r.0, 0 (Virtual) // 0 KB
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//
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// Store different patterns to the 4 test locations. This should cause
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// values to be stored in the L2 cache and memory.
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//
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LWI (Pattern, Pattern4) // L2_Cache[768K] = Pattern4;
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stwx Pattern, r.9, Offset
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LWI (Pattern, Pattern3) // L2_Cache[512K] = Pattern3;
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stw Pattern, 0 (r.9)
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LWI (Pattern, Pattern2) // L2_Cache[256K] = Pattern2;
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stwx Pattern, Virtual, Offset
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LWI (Pattern, Pattern1) // L2_Cache[ 0K] = Pattern1;
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stw Pattern, 0 (Virtual)
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//
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// Disable the L2 cache. The tags are NOT invalidated. No L2 snoop
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// operations or data updates are performed.
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//
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.0, 0xCFC(ISA)
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rlwinm r.0, r.0, 0, ~(L2_EN+L2_UPDATE_EN)
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stw r.0, 0xCFC(ISA)
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sync
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//
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// Store PATTERN0 to our 4 test locations. Only L1 and main memory will be
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// written since the L2 cache has been disabled. This allows us to distinguish
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// patterns in the L2 from main memory.
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//
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LWI (Pattern, Pattern0) // L2_Cache[768K] = Pattern0;
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stwx Pattern, r.9, Offset
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stw Pattern, 0 (r.9) // L2_Cache[512K] = Pattern0;
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stwx Pattern, Virtual,Offset // L2_Cache[256K] = Pattern0;
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stw Pattern, 0 (Virtual) // L2_Cache[ 0K] = Pattern0;
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//
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// Load 8 locations (for an 8-way L1 cache) 4096 bytes apart in order to flush
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// the test locations from the L1. We can't use DCBF since that would flush
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// the L2 also.
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//
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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lwzu Pattern, 4096(Virtual)
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LWI (Virtual, VIRTUAL)
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//
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// Re-enable the L2 cache
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//
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.0, 0xCFC(ISA)
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oris r.0, r.0, ((L2_EN + L2_UPDATE_EN) >> 16)
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stw r.0, 0xCFC(ISA)
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sync
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lwz Pattern, 0(Virtual) // Read test location @ 0 KB
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lwzx r.0, Virtual, Offset // Read test location @ 256 KB
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rlwimi Pattern, r.0, 0, 8, 15
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lwz r.0, 0 (r.9) // Read test location @ 512 KB
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rlwimi Pattern, r.0, 0, 16, 23
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lwzx r.0, r.9, Offset // Read test location @ 768 KB
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rlwimi Pattern, r.0, 0, 24, 31
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//
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// Test the pattern from L2 to determine it's size
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//
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LWI (r.0, 0x11777777)
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cmpl 0,0, Pattern, r.0
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beq Set_256K
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LWI (r.0, 0x11227777)
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cmpl 0,0, Pattern, r.0
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beq Set_512K
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LWI (r.0, 0x11223344)
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cmpl 0,0, Pattern, r.0
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beq Set_1M
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// LWI (r.0, 0x77777777)
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// cmpl 0,0, Pattern, r.0
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// bne InvalidPattern
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li CacheSize, 0
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b DisableCache
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//
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// Unexpected pattern. Return it for display.
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//
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InvalidPattern:
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// mr CacheSize, Pattern // Not needed if CacheSize == Pattern
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b DisableCache
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Set_256K:
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li CacheSize, 256
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li r.4, L2_256K
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b SetCacheSize
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Set_512K:
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li CacheSize, 512
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li r.4, L2_512K
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b SetCacheSize
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Set_1M:
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li CacheSize, 1024
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li r.4, L2_1M
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//
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// r.3 = cache size in KB
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// r.4 = cache size field to be inserted into Eagle register AC.
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//
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SetCacheSize:
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.9, 0xCFC(ISA)
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rlwimi r.9, r.4, 0, CF_L2_SIZE // Insert CF_L2_SIZE field
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stw r.9, 0xCFC(ISA)
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sync
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//
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// Eagle 2.1 BUG:
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// Write-back works OK
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// Write-thru walks thru addresses but does not invalidate them.
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// Don't need to flush for write-thru anyway!!!!
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//
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// NOTE: If changing from WRITE-BACK to WRITE-THROUGH, you must flush
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// beforehand because castouts are not supported in write-through.
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// If the L2 has dirty data, then switching to write-through, the
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// dirty data won't get flushed (cast out) to main memory.
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//
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rlwinm r.4, r.9, 0, 1,31 // Clear L2_UPDATE_EN (lock L2)
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stw r.4, 0xCFC(ISA)
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oris r.0, r.4, (CF_FLUSH_L2 >> 16) // Toggle CF_FLUSH_L2
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sync
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stw r.0, 0xCFC(ISA)
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sync
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stw r.4, 0xCFC(ISA)
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//
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// Flush the L2 by walking through memory (2x L2 size)
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//
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rlwinm r.0, CacheSize, 10-5+1, 0, 31 // L2Size * (1024 / LINE_SIZE) * 2
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mtctr r.0
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subi r.4, Virtual, L2_LINE_SIZE
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FlushLoop:
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lwzu r.0, L2_LINE_SIZE (r.4)
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bdnz FlushLoop
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//
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// Disable the L2 cache
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//
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DisableCache:
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sync
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lwz r.9, 0xCFC(ISA)
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rlwinm r.9, r.9, 0, ~(L2_EN+L2_UPDATE_EN)
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stw r.9, 0xCFC(ISA)
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sync
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stw EagleA8, 0xCF8(ISA)
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sync
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stw L2off, 0xCFC(ISA) // Disable the L2 cache
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sync
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//
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// Restore the original contents of the test locations
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//
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lwz Restore,[toc].LRDATA(rtoc)
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lwz r0, 0(Restore) // Restore test location 0
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stw r0, 0(Virtual)
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lwz r0, 4(Restore) // Restore test location 1
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stwux r0, Virtual, Offset
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lwz r0, 8(Restore) // Restore test location 2
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stwux r0, Virtual, Offset
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lwz r0,12(Restore) // Restore test location 3
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stwx r0, Virtual, Offset
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li r.0, 0 // Invalidate the BAT we used
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mtdbatu BAT_REG, r.0
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mtdbatl BAT_REG, r.0
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L2_Exit:
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mfspr r.0, HID0
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rlwinm r.0, r.0, 0, ~0x2000 // Unlock the Icache
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mtspr HID0, r.0
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LEAF_EXIT(HalpSizeL2)
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//***********************************************************************
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//
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// Synopsis:
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// VOID HalpFlushAndDisableL2(VOID)
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//
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// Purpose:
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// If the L2 is enabled and in WRITE-BACK mode, the L2 is flushed.
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// In either mode, the L2 is invalidated, and upon exit, the L2 is
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// left disabled.
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//
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// Returns:
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// nothing
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//
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// Global Variables Referenced:
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// HalpIoControlBase
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//
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// NOTE: Interrupts are assumed to be disabled upon entry.
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//***********************************************************************
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LEAF_ENTRY(HalpFlushAndDisableL2)
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mfsprg r.12, 1 // Get PCR->SecondLevelDcacheSize
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lwz r.0, PcSecondLevelDcacheSize (r.12)
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srwi. r.0, r.0, 5 // # lines in L2
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beqlr-
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mtctr r.0
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lwz ISA,[toc]HalpIoControlBase(r.toc) // Get base of ISA I/O
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lwz ISA,0(ISA)
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LWI (EagleA8, 0x800000A8) // Processor Interface Configuration 1
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addi EagleAC, EagleA8, 4 // Processor Interface Configuration 2
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stw EagleAC, 0xCF8(ISA)
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sync
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lwz r.5, 0xCFC(ISA)
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andis. r.0, r.5, (L2_EN >> 16) // Disable the L2 (L2_EN = 0)
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beqlr
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mfspr r.9, HID0 // Lock the Icache
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ori r.0, r.9, 0x2000
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mtspr HID0, r.0
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isync
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stw EagleA8, 0xCF8(ISA) // Check CF_L2_MP
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sync
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lwz r.4, 0xCFC(ISA)
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andi. r.0, r.4, CF_L2_MP
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beq FlushExit // Return if L2 is disabled
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cmpwi r.0, CF_WRITE_THRU // Is L2 in write-through mode ?
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beq InvalidateL2 // Yes, then flush is not necessary
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//
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// Flush the L2 contents to main memory
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//
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stw EagleAC, 0xCF8(ISA) // Clear L2_UPDATE_EN (lock L2)
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rlwinm r.0, r.5, 0, 1,31
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oris r.0, r.0, (CF_FLUSH_L2 >> 16) // Toggle CF_FLUSH_L2
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stw r.0, 0xCFC(ISA)
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sync
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stw r.5, 0xCFC(ISA)
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InvalidateL2:
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stw EagleAC, 0xCF8(ISA) // Clear L2_UPDATE_EN (lock L2)
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sync
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rlwinm r.5, r.5, 0, 2,0 // Clear L2_EN (disable the L2 cache)
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ori r.0, r.5, CF_INV_MODE // Set L2 to invalidate mode
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stw r.0, 0xCFC(ISA)
|
|
sync
|
|
|
|
//
|
|
// Invalidate the L2 by walking thru memory
|
|
//
|
|
LWI (r.12, 0x80000000-L2_LINE_SIZE)
|
|
Invalidate:
|
|
lwzu r.0, L2_LINE_SIZE (r.12)// Read from L2 cache
|
|
bdnz Invalidate
|
|
|
|
|
|
stw EagleA8, 0xCF8(ISA)
|
|
sync
|
|
rlwinm r.4, r.4, 0, ~CF_L2_MP // Clear CF_L2_MP
|
|
stw r.4, 0xCFC(ISA)
|
|
|
|
FlushExit:
|
|
stw EagleAC, 0xCF8(ISA)
|
|
sync
|
|
rlwinm r.5, r.5, 0, 2,31 // Clear L2_EN & L2_UPDATE_EN
|
|
stw r.5, 0xCFC(ISA) // Clear CF_INV_MODE
|
|
|
|
|
|
mtspr HID0, r.9 // Unlock the Icache
|
|
|
|
LEAF_EXIT(HalpFlushAndDisableL2)
|
|
|
|
|
|
.LRDATA:
|
|
// loc 0 - Holds memory at 0K
|
|
.ualong 0x0
|
|
// loc 4 - Holds memory at 256K
|
|
.ualong 0x0
|
|
// loc 8 - Holds memory at 512K
|
|
.ualong 0x0
|
|
// loc 12 - Holds memory at 1024K
|
|
.ualong 0x0
|
|
|