595 lines
35 KiB
C
595 lines
35 KiB
C
//
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// Defines for Access to the MP Agent
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// this file can be used on assembly language files and C Files
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//
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#ifndef _MPAGENT_H_
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#define _MPAGENT_H_
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#define MPA_BASE_ADDRESS 0xbffff000 /* Base to address the MP_Agent */
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#define MPA_BOOT_MESSAGE 6 /* to start the other processors */
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#define MPA_KERNEL_MESSAGE 10 /* kernel requested IPI */
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#define MPA_TIMER_MESSAGE 11 /* timer interrupt */
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#define MPA_RESTART_MESSAGE 12 /* restart requested */
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//
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// define relative offsets of the MP Agent registers
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// (little endian mode)
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//
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#define MPA_cpureg 0x000 // (0x00 * 8) configuration cpu register
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#define MPA_cpuda1reg 0x008 // (0x01 * 8) general register
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#define MPA_msgdata 0x010 // (0x02 * 8) data for message passing
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#define MPA_msgstatus 0x018 // (0x03 * 8) message status
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#define MPA_snooper 0x020 // (0x04 * 8) snooper configuration register
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#define MPA_tagreg 0x028 // (0x05 * 8) tag ram R/W index register
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#define MPA_snpadreg 0x030 // (0x06 * 8) adress of first MBus fatal error
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#define MPA_itpend 0x038 // (0x07 * 8) Interrupt register
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#define MPA_datamsg1 0x040 // (0x08 * 8) data message register 1
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#define MPA_datamsg2 0x048 // (0x09 * 8) data message register 2
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#define MPA_datamsg3 0x050 // (0x0a * 8) data message register 3
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#define MPA_lppreg0 0x058 // (0x0b * 8) LPP register cpu 0
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#define MPA_lppreg1 0x060 // (0x0c * 8) LPP register cpu 1
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#define MPA_lppreg2 0x068 // (0x0d * 8) LPP register cpu 2
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#define MPA_lppreg3 0x070 // (0x0e * 8) LPP register cpu 3
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#define MPA_tagram 0x078 // (0x0f * 8) tag ram R/W register
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#define MPA_crefcpt 0x080 // (0x10 * 8) cpu general read counter register
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#define MPA_ctarcpt 0x088 // (0x11 * 8) cpu programmable access counter
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#define MPA_srefcpt 0x090 // (0x12 * 8) snooper general read counter reg.
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#define MPA_starcpt 0x098 // (0x13 * 8) snooper programmable accesscounter
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#define MPA_linkreg 0x0a0 // (0x14 * 8) link register
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#define MPA_software1 0x0a8 // (0x15 * 8) software register1
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#define MPA_msgaddress 0x0b0 // (0x16 * 8) address message register
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#define MPA_mem_operator 0x0b8 // (0x17 * 8) operator internal burst register
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#define MPA_software2 0x0c0 // (0x18 * 8) software register2
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/* +---------------------------+ */
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/* ! cpureg register (0x00) ! */
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/* +---------------------------+ */
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/*
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The CPUREG Register (LOW-PART) , which has the following bits:
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15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0
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+---------------|---------------|---------------|---------------+
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| ED| ED| ED| | MI| MI| MI| EI| EI| EI| EI| EI| EI| R | 1 | 0 | 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|__________ enable shared 1-> TagCopy for S
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|_____________ enable message sending
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|_________________ reserved
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|_____________________ enable external Interrupts
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|________________________ enable external Interrupts
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|____________________________ enable external Interrupts
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|________________________________ enable external Interrupts
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|____________________________________ enable external Interrupts
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|__________________________________________ enable external Interrupts
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|______________________________________________ enable Message Reg. Int.
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|__________________________________________________ enable Message Reg. Int.
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|______________________________________________________ enable Message Reg. Int.
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|__________________________________________________________
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|______________________________________________________________ Edge Config for Interrupts
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|__________________________________________________________________ Edge Config for Interrupts
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|______________________________________________________________________ Edge Config for Interrupts
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The CPUREG Register (HIGH-PART), which has the following bits:
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31 30 29 28 27 26 25 24| 23 22 21 20 19 18 17 16
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+---------------|---------------|---------------|---------------+
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| 1 | 1 | 1 | 1 | 1 | MA| MA| MA| MA| MA| MA| MA| ED| ED| ED| ED| 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ Edge Config for Interrupts
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|_____________ Edge Config for Interrupts
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|________________ Edge Config for Interrupts
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|____________________ Edge Config for Interrupts
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|________________________ Interrupt Mask on external Request
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|____________________________ Interrupt Mask on external Request
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|________________________________ Interrupt Mask on external Request
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|____________________________________ Interrupt Mask on external Request
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|__________________________________________ Interrupt Mask on external Request
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|______________________________________________ Interrupt Mask on external Request
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|__________________________________________________ Interrupt Mask on external Request
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|______________________________________________________ maximal Retry Count on MP-Bus
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|__________________________________________________________ maximal Retry Count on MP-Bus
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|______________________________________________________________ maximal Retry Count on MP-Bus
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|__________________________________________________________________ maximal Retry Count on MP-Bus
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|______________________________________________________________________ maximal Retry Count on MP-Bus
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*/
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#define MPA_ENSHARED 0x00000001 /* (0) If the MP_Agent has not the data in
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* exclusif state, the MP_Agent forces
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* the data to shared state for all
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* coherent access.
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*
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* (1) If no other MP_agent has the data
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* in exclusif state, the requester
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* can put the data in share or exclusif
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* state.
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*/
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#define MPA_ENSENDMSG 0x00000002 /* (1) 0 -> disable message passing
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* 1 -> enable message passing
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*/
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#define MPA_ENINT_MASK 0x00001ffc /* (12:2) enable interrupt mask */
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#define MPA_ENINT_MASKSHIFT 3 /* shift for enable interrupt mask */
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#define MPA_ENINT_SR_IP3 0x00000008 /* (3) enable external interrupt SR_IP3 */
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#define MPA_ENINT_SR_IP4 0x00000010 /* (4) enable external interrupt SR_IP4 */
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#define MPA_ENINT_SR_IP5 0x00000020 /* (5) enable external interrupt SR_IP5 */
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#define MPA_ENINT_SR_IP6 0x00000040 /* (6) enable external interrupt SR_IP6 */
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#define MPA_ENINT_SR_IP7 0x00000080 /* (7) enable external interrupt SR_IP7 */
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#define MPA_ENINT_SR_IP8 0x00000100 /* (8) enable external interrupt SR_IP8 */
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#define MPA_ENINT_ITMSG1 0x00000200 /* (9) enable interrupt message1 register */
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#define MPA_ENINT_ITMSG2 0x00000400 /* (10) enable interrupt message2 register */
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#define MPA_ENINT_ITMSG3 0x00000800 /* (11) enable interrupt message3 register */
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#define MPA_ENINT_MPBERR 0x00001000 /* (12) enable interrupt MP_Agent fatal error */
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#define MPA_INTCONF_MASK 0x000fe000 /* (19:13) select interrupt level
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* 0 -> falling
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* 1 -> raising */
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#define MPA_INTCONF_SR_IP3 0x00002000 /* (13) select raising mode for SR_IP3 */
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#define MPA_INTCONF_SR_IP4 0x00004000 /* (14) select raising mode for SR_IP4 */
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#define MPA_INTCONF_SR_IP5 0x00008000 /* (15) select raising mode for SR_IP5 */
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#define MPA_INTCONF_SR_IP6 0x00010000 /* (16) select raising mode for SR_IP6 */
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#define MPA_INTCONF_SR_IP7 0x00020000 /* (17) select raising mode for SR_IP7 */
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#define MPA_INTCONF_SR_IP8 0x00040000 /* (18) select raising mode for SR_IP8 */
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#define MPA_INTCONF_SR_NMI 0x00080000 /* (19) select raising mode for SR_NMI */
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#define MPA_INTMSK 0x07f00000 /* (26:20) mask sent during external request stage */
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#define MPA_MAXRTY_MASK 0xf8000000 /* (31:27) mask for maximum number of retry on
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* INV / UPD / MESS / RD_COH */
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/* +---------------------------+ */
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/* ! cpuda1reg register (0x01) ! */
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/* +---------------------------+ */
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/*
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The CPU1REG Register (LOW-PART) , which has the following bits:
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15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0
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+---------------|---------------|---------------|---------------+
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| SS| SS| TI| 1 | DP| DP| R | R | R | R | R | R | R | R | R | R | 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ reserved
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|_____________ reserved
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|________________ reserved
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|____________________ reserved
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|________________________ reserved
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|____________________________ reserved
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|________________________________ reserved
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|____________________________________ reserved
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|__________________________________________ reserved
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|______________________________________________ reserved
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|__________________________________________________ CPU Data Pattern
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|______________________________________________________ CPU Data Pattern
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|__________________________________________________________ Int. Update Policy 0 - direct
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|______________________________________________________________ Test Interrupts
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|__________________________________________________________________ Cpu Port Statistics
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|______________________________________________________________________ Cpu Port Statistics
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The CPU1REG Register (HIGH-PART), which has the following bits:
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31 30 29 28 27 26 25 24| 23 22 21 20 19 18 17 16
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+---------------|---------------|---------------|---------------+
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| R | R | R | R | R | R | R | R | R | R | R | IS| IS| IS| 1 | SS| 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ Cpu Port Statistics
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|_____________ Enable Read Anticipate mode
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|________________ Select Interrupt for Internal Ints
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|____________________ Select Interrupt for Internal Ints
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|________________________ Select Interrupt for Internal Ints
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|____________________________ reserved
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|________________________________ reserved
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|____________________________________ reserved
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|__________________________________________ reserved
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|______________________________________________ reserved
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|__________________________________________________ reserved
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|______________________________________________________ reserved
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|__________________________________________________________ reserved
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|______________________________________________________________ reserved
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|__________________________________________________________________ reserved
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|______________________________________________________________________ reserved
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*/
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#define MPA_CPURDPAT_MASK 0x00000c00 /* (11:10) number of wait-state between 2 double
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* cpu reads. */
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#define MPA_CPURDPAT_DD 0x00000000 /* 0 : dd */
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#define MPA_CPURDPAT_DDX 0x00000400 /* 1 : dd. */
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#define MPA_CPURDPAT_DDXX 0x00000800 /* 2 : dd.. */
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#define MPA_CPURDPAT_DXDX 0x00000c00 /* 3 : d.d. */
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#define MPA_ENDIRECT 0x00001000 /* (12) 0 send interrupt to all MP_Agent
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* 1 use LPP mechanism to dispatch interrupt
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*/
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#define MPA_ENTESTIT 0x00002000 /* (13) 0 disable test mode (interrupts from MPBus)
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* 1 enable test mode (interrupts from INTCONF(6:0))
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*/
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#define MPA_CPUSELSTAT_MASK 0x0001c000 /* (16:14) select programmable mode for cpu
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* access
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*/
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#define MPA_ENRDANT 0x00020000 /* (17) 0 disable overlapping memory/MP_Agent
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*
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* 1 enable overlapping memory/MP_Agent
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* The Tag copy checking is done concurently
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* with memory access. The memory must support
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* the 'read abort' command (not supported
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* by current Asic chipset rev.0).
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*/
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#define MPA_SELITI_MASK 0x001c0000 /* (20:18) define routage for internal interrupts */
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#define MPA_SELITI_SR_IP3 0x00000000 /* Internal interrupts go on SR_IP3 */
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#define MPA_SELITI_SR_IP4 0x00040000 /* Internal interrupts go on SR_IP4 */
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#define MPA_SELITI_SR_IP5 0x00080000 /* Internal interrupts go on SR_IP5 */
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#define MPA_SELITI_SR_IP6 0x000c0000 /* Internal interrupts go on SR_IP6 */
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#define MPA_SELITI_SR_IP7 0x00100000 /* Internal interrupts go on SR_IP7 */
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#define MPA_SELITI_SR_IP8 0x00140000 /* Internal interrupts go on SR_IP8 */
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/* +---------------------------+ */
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/* ! msgstatus register (0x03) ! */
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/* +---------------------------+ */
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/* message passing status register */
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#define MPA_VALSTAT 0x00000001 /* (0) 0 -> status is invalid
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* 1 -> status is valid */
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//
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// if (MPA_VALSTAT != 0)
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//
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#define MPA_SENDMSG 0x00000002 /* (1) 1 -> message not acknowledged by MPBus */
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#define MPA_ERRMSG 0x00000004 /* (2) 0 -> message has been acknowledged
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* 1 -> at least one MP_Agent has refused */
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#define MPA_BUSY 0x00000008
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#define MPA_ADERR_MASK 0x000000f0 /* (7:4) list of refusing processor(s) */
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#define MPA_ADERR_SHIFT 0x4
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/* +---------------------------+ */
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/* ! snooper register (0x04) ! */
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/* +---------------------------+ */
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/*
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The SNOOPER Register (LOW-PART), which has the following bits:
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15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0
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+---------------|---------------|---------------|---------------+
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| 1 | R | R | R | R | - | - | - | 1 | 1 | 1 | - | - | R | R | 1 | 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ enable Message receive
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|_____________ reserved
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|________________ reserved
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|____________________ LineSize
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|________________________ LineSize
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|____________________________ Three/ Two Party
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|________________________________ enable Read+Link
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|____________________________________ enable Coherency
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|__________________________________________ MP Statistics
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|______________________________________________ MP Statistics
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|__________________________________________________ MP Statistics
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|______________________________________________________ reserved
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|__________________________________________________________ reserved
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|______________________________________________________________ reserved
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|__________________________________________________________________ reserved
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|______________________________________________________________________ FATAL INTERRUPT inactive
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The SNOOPER Register (HIGH-PART), which has the following bits:
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31 30 29 28 27 26 25 24| 23 22 21 20 19 18 17 16
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+---------------|---------------|---------------|---------------+
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| 1 | 1 | 1 | 1 | 1 | R | R | R | R | R | M | M | M | C | C | C | 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ Cderrtag TagSeq direct error code
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|_____________ Cderrtag
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|________________ Cderrtag
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|____________________ Mderrtag SnpTagSeq memo Error code
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|________________________ Mderrtag
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|____________________________ Mderrtag
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|________________________________ reserved
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|____________________________________ reserved
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|__________________________________________ reserved
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|______________________________________________ reserved
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|__________________________________________________ reserved
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|______________________________________________________ Agent Address
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|__________________________________________________________ Agent Address
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|______________________________________________________________ seq. cpu error
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|__________________________________________________________________ tag seq. error
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|______________________________________________________________________ ext. seq. error
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*/
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#define MPA_ENRCVMESS 0x00000001 /* (0) 0 -> disable message receiving
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* 1 -> enable message receiving */
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#define MPA_LSIZE_MASK 0x00000018 /* (4:3) secondary linesize mask */
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#define MPA_LSIZE16 0x00000000 /* secondary linesize = 16 bytes */
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#define MPA_LSIZE32 0x00000008 /* secondary linesize = 32 bytes */
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#define MPA_LSIZE64 0x00000010 /* secondary linesize = 64 bytes */
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#define MPA_LSIZE128 0x00000018 /* secondary linesize = 128 bytes */
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/* NOTE: MP_Agent doesn't support linesize greater than 64 bytes !! */
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#define MPA_DISTPARTY 0x00000020 /* (5) 0 -> enable three-party mode
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* MP_Agent requester/MP_Agent target
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* + memory (for update)
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*
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* 1 -> disable three-party mode
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* MP_Agent requester/MP_Agent target
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*/
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#define MPA_ENLINK 0x00000040 /* (6) 0 -> The cpu read and link command is
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* disabled.
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* 1 -> The cpu read and link command is
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* enabled.
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*/
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#define MPA_ENCOHREQ 0x00000080 /* (7) 0 -> disable sending external request
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* for coherency to cpu by his MP_Agent
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* 1 -> enable sending external request
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* for coherency to cpu by his MP_Agent
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*/
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#define MPA_SNPSELSTAT_MASK 0x00000700 /* (10:8) select programmable mode for snooper
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* access
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*/
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#define MPA_RSTSNPERR 0x00008000 /* (15) 1 -> reset all MP bus fatal error
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*
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* 0 -> enable new fatal error on MP bus
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* sent by interrupt.
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*/
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#define MPA_CDERRTAG 0x00070000 /* (18:16) (Read only) error code */
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#define MPA_MCDERRTAG 0x00380000 /* (21:19) (Read only) error code */
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#define MPA_MCDERREXT 0x00c00000 /* (23:22) (Read only) error code */
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#define MPA_ADAGT_MASK 0x18000000 /* (28:27) (Read only) MP_Agent address mask */
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#define MPA_ADAGT_SHIFT 27 /* shift address agent value */
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#define MPA_MSEQERR 0xe0000000 /* (31:29) (Read only) error code */
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#define MPA_RETRYERR 0x20000000 /* (31:29) (Read only) error code */
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/* +---------------------------+ */
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/* ! itpend register (0x07) ! */
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/*+---------------------------+ */
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/*
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The Interrupt Pending Register (LOW-PART) , which has the following bits:
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15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0
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+---------------|---------------|---------------|---------------+
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| UE| UE| UE| UE| R | F | M | M | M | R | E | E | E | E | E | E | 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ pending external Interrupts
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|_____________ pending external Interrupts
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|________________ pending external Interrupts
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|____________________ pending external Interrupts
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|________________________ pending external Interrupts
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|____________________________ pending external Interrupts
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|________________________________ reserved
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|____________________________________ Message Register 1
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|__________________________________________ Message Register 2
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|______________________________________________ Message Register 3
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|__________________________________________________ FATAL MP Agent Error
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|______________________________________________________ reserved
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|__________________________________________________________ last updated external State
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|______________________________________________________________ last updated external State
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|__________________________________________________________________ last updated external State
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|______________________________________________________________________ last updated external State
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The Interrupt Pending Register (HIGH-PART), which has the following bits:
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31 30 29 28 27 26 25 24| 23 22 21 20 19 18 17 16
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+---------------|---------------|---------------|---------------+
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| R | R | R | R | R | R | R | R | R | UF| UM| UM| UM| R | UE| UE| 0 Low Activ; 1 High activ;
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+---------------|---------------+---------------|---------------+
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|_________ last updated external State
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|_____________ last updated external State
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|________________ reserved
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|____________________ last updated Message State
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|________________________ last updated Message State
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|____________________________ last updated Message State
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|________________________________ last updated FATAL E State
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|____________________________________ reserved
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|__________________________________________ reserved
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|______________________________________________ reserved
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|__________________________________________________ reserved
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|______________________________________________________ reserved
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|__________________________________________________________ reserved
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|______________________________________________________________ reserved
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|__________________________________________________________________ reserved
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|______________________________________________________________________ reserved
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*/
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/* external interrupts */
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#define MPA_INTN_MASKGEN 0x000007ff /* (10:0) pending general interrupt mask */
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#define MPA_INTN_EXT_MASK 0x0000003f /* (5:0) pending external interrupt mask */
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#define MPA_INTN_SR_IP3 0x00000001 /* (0) pending external interrupt SR_IP3 */
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#define MPA_INTN_SR_IP4 0x00000002 /* (1) pending external interrupt SR_IP4 */
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#define MPA_INTN_SR_IP5 0x00000004 /* (2) pending external interrupt SR_IP5 */
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#define MPA_INTN_SR_IP6 0x00000008 /* (3) pending external interrupt SR_IP6 */
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#define MPA_INTN_SR_IP7 0x00000010 /* (4) pending external interrupt SR_IP7 */
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#define MPA_INTN_SR_IP8 0x00000020 /* (5) pending external interrupt SR_IP8 */
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/* internal interrupts */
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#define MPA_INTN_ITNMI 0x00000040 /* (6) unused */
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#define MPA_INTN_ITMSG1 0x00000080 /* (7) pending interrupt message1 register */
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#define MPA_INTN_ITMSG2 0x00000100 /* (8) pending interrupt message2 register */
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#define MPA_INTN_ITMSG3 0x00000200 /* (9) pending interrupt message3 register */
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#define MPA_INTN_MPBERR 0x00000400 /* (10) pending interrupt MP_Agent fatal error */
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/* pending internal interrupts mask */
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#define MPA_INTN_INT_MASK (MPA_INTN_ITNMI | \
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MPA_INTN_ITMSG1 | \
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MPA_INTN_ITMSG2 | \
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MPA_INTN_ITMSG3 | \
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MPA_INTN_MPBERR)
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/* old interrupts written in the processor cause register */
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/* external interrupts */
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#define MPA_OINTN_MASKGEN 0x007ff000 /* (22:12) old general interrupt mask */
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#define MPA_OINTN_SHIFT 12 /* shift to compare to pending interrupt */
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#define MPA_OINTN_MASK 0x0003f000 /* (17:12) old external interrupt mask */
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#define MPA_OINTN_SR_IP3 0x00001000 /* (12) old external interrupt SR_IP3 */
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#define MPA_OINTN_SR_IP4 0x00002000 /* (13) old external interrupt SR_IP4 */
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#define MPA_OINTN_SR_IP5 0x00004000 /* (14) old external interrupt SR_IP5 */
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#define MPA_OINTN_SR_IP6 0x00008000 /* (15) old external interrupt SR_IP6 */
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#define MPA_OINTN_SR_IP7 0x00010000 /* (16) old external interrupt SR_IP7 */
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#define MPA_OINTN_SR_IP8 0x00020000 /* (17) old external interrupt SR_IP8 */
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/* internal interrupts */
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#define MPA_OINTN_ITNMI 0x00040000 /* (18) unused */
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#define MPA_OINTN_ITMSG1 0x00080000 /* (19) old interrupt message1 register */
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#define MPA_OINTN_ITMSG2 0x00100000 /* (20) old interrupt message2 register */
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#define MPA_OINTN_ITMSG3 0x00200000 /* (21) old interrupt message3 register */
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#define MPA_OINTN_MPBERR 0x00400000 /* (22) old interrupt MP_Agent fatal error */
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/* +---------------------------+ */
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/* ! msgaddress register(0x16) ! */
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/* +---------------------------+ */
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/* Message address for message passing */
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#define MPA_CPUTARGET_MASK 0x0000000f /* (3:0) target cpu mask */
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#define MPA_CPUTARGET_ALL 0x0000000f /* cpu target : all */
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#define MPA_CPUTARGET_CPU0 0x00000001 /* cpu target : 0 */
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#define MPA_CPUTARGET_CPU1 0x00000002 /* cpu target : 1 */
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#define MPA_CPUTARGET_CPU2 0x00000004 /* cpu target : 2 */
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#define MPA_CPUTARGET_CPU3 0x00000008 /* cpu target : 3 */
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#define MPA_REGTARGET_MASK 0x000001f0 /* (8:4) target register */
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#define MPA_REGTARGET_MSG1 0x00000080 /* msg1reg target register */
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#define MPA_REGTARGET_MSG2 0x00000090 /* msg2reg target register */
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#define MPA_REGTARGET_MSG3 0x000000a0 /* msg3reg target register */
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#define MPA_ENMSGLPP 0x00000200 /* (9) 0 disable LPP mode for message passing */
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/* +---------------------------+ */
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/* ! mem_operator reg. (0x17) ! */
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/* +---------------------------+ */
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/* For fake read on a 4Mb segment. Used for cache replace functions */
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#define MPA_OP_ENABLE 0x00000001 /* (0) 0 disable operator (address invalid)
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* 1 enable operator (address valid)
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*/
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#define MPA_OP_ADDR_MASK 0xffc00000 /* (31:22) base physical address of a 4Mb kseg0
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* reserved segment (4Mb == 0x00400000).
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*/
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#define MPA_TAGREG_ADDR_MASK 0x003ffff0
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#define MPA_TR_STATE_MASK 0x00000003
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#define MPA_TR_NOCOHERENT 0x00000000
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/*
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* Number of retries before sending a fatal error
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*/
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#define MPA_MSG_RETRY 10
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typedef struct _mp_agent{
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/* Register Register
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* name number offset description
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* ---------- ---- ------ --------------------------------- */
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ULONG cpureg; /* 0x00 0x000 configuration cpu register */
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ULONG invalid_0;
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ULONG cpuda1reg; /* 0x01 0x008 general register */
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ULONG invalid_1;
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ULONG msgdata; /* 0x02 0x010 data for message passing */
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ULONG invalid_2;
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ULONG msgstatus; /* 0x03 0x018 message status */
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ULONG invalid_3;
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ULONG snooper; /* 0x04 0x020 snooper configuration register */
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ULONG invalid_4;
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ULONG tagreg; /* 0x05 0x028 tag ram R/W index register */
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ULONG invalid_5;
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ULONG snpadreg; /* 0x06 0x030 adress of first MBus fatal error */
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ULONG invalid_6;
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ULONG itpend; /* 0x07 0x038 Interrupt register */
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ULONG invalid_7;
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ULONG datamsg1; /* 0x08 0x040 data message register 1 */
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ULONG invalid_8;
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ULONG datamsg2; /* 0x09 0x048 data message register 2 */
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ULONG invalid_9;
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ULONG datamsg3; /* 0x0a 0x050 data message register 3 */
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ULONG invalid_a;
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ULONG lppreg0; /* 0x0b 0x058 LPP register cpu 0 */
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ULONG invalid_b;
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ULONG lppreg1; /* 0x0c 0x060 LPP register cpu 1 */
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ULONG invalid_c;
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ULONG lppreg2; /* 0x0d 0x068 LPP register cpu 2 */
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ULONG invalid_d;
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ULONG lppreg3; /* 0x0e 0x070 LPP register cpu 3 */
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ULONG invalid_e;
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ULONG tagram; /* 0x0f 0x078 tag ram R/W register */
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ULONG invalid_f;
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ULONG crefcpt; /* 0x10 0x080 cpu general read counter register */
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ULONG invalid_10;
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ULONG ctarcpt; /* 0x11 0x088 cpu programmable access counter */
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ULONG invalid_11;
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ULONG srefcpt; /* 0x12 0x090 snooper general read counter reg. */
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ULONG invalid_12;
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ULONG starcpt; /* 0x13 0x098 snooper programmable accesscounter*/
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ULONG invalid_13;
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ULONG linkreg; /* 0x14 0x0a0 link register */
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ULONG invalid_14;
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ULONG software1; /* 0x15 0x0a8 software register1 */
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ULONG invalid_15;
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ULONG msgaddress; /* 0x16 0x0b0 address message register */
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ULONG invalid_16;
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ULONG mem_operator; /* 0x17 0x0b8 operator internal burst register */
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ULONG invalid_17;
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ULONG software2; /* 0x18 0x0c0 software register2 */
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}MP_AGENT, *PMP_AGENT;
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#define mpagent ((volatile PMP_AGENT) MPA_BASE_ADDRESS) // mpagent address
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#endif
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