697 lines
18 KiB
C
697 lines
18 KiB
C
// TODO:
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// (3) Should registers be treated as 64 or 32bit? Note that Fregs are
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// 64bits only. -- All registers should be treated as 64bit values
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// since LDQ/EXTB is done for byte fetches (stores); the intermediate
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// values could be hidden.
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#define FALSE 0
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#define TRUE 1
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#define STATIC static
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#include "ntsdp.h"
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#include <alphaops.h>
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#include "ntdis.h"
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#include "ntreg.h"
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#include "optable.h"
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void BlankFill(ULONG);
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void OutputHex(ULONG, ULONG, BOOLEAN);
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void OutputEffectiveAddress(ULONG);
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void OutputString(char *);
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void OutputReg(ULONG);
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void OutputFReg(ULONG);
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void GetNextOffset(PADDR, BOOLEAN);
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BOOLEAN fDelayInstruction(void);
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ALPHA_INSTRUCTION disinstr;
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extern PUCHAR pszReg[];
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extern BOOLEAN GetMemDword(PADDR, PULONG);
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BOOLEAN disasm(PADDR, PUCHAR, BOOLEAN);
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STATIC char *pBufStart;
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STATIC char *pBuf;
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#define OPRNDCOL 27 // Column for first operand
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#define EACOL 40 // column for effective address
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#define FPTYPECOL 40 // .. for the type of FP instruction
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BOOLEAN
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disasm (PADDR poffset, PUCHAR bufptr, BOOLEAN fEAout)
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{
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ULONG opcode;
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ULONG Ea; // Effective Address
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POPTBLENTRY pEntry;
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pBufStart = pBuf = bufptr; // Initialize pointers to buffer that
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// will receive the disassembly text
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OutputHex(Flat(*poffset), 8, FALSE);// Output Hex address of instruction
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*pBuf++ = ':';
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*pBuf++ = ' ';
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if (!GetMemDword(poffset, &disinstr.Long)) {
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OutputString("???????? ????\n");
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*pBuf = '\0';
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return(FALSE);
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}
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OutputHex(disinstr.Long, 8, FALSE); // Output instruction in Hex
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*pBuf++ = ' ';
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opcode = disinstr.Memory.Opcode; // Select disassembly procedure from
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pEntry = findOpCodeEntry(opcode); // Get non-func entry for this code
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switch (pEntry->iType) {
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case ALPHA_UNKNOWN:
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OutputString(pEntry->pszAlphaName);
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break;
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case ALPHA_MEMORY:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.Memory.Ra);
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*pBuf++ = ',';
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OutputHex(disinstr.Memory.MemDisp, (WIDTH_MEM_DISP + 3)/4, TRUE );
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*pBuf++ = '(';
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OutputReg(disinstr.Memory.Rb);
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*pBuf++ = ')';
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break;
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case ALPHA_FP_MEMORY:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputFReg(disinstr.Memory.Ra);
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*pBuf++ = ',';
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OutputHex(disinstr.Memory.MemDisp, (WIDTH_MEM_DISP + 3)/4, TRUE );
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*pBuf++ = '(';
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OutputReg(disinstr.Memory.Rb);
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*pBuf++ = ')';
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break;
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case ALPHA_MEMSPC:
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OutputString(findFuncName(pEntry, disinstr.Memory.MemDisp & BITS_MEM_DISP));
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//
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// Some memory special instructions have an operand
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//
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switch (disinstr.Memory.MemDisp & BITS_MEM_DISP) {
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case FETCH_FUNC:
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case FETCH_M_FUNC:
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// one operand, in Rb
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BlankFill(OPRNDCOL);
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*pBuf++ = '0';
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*pBuf++ = '(';
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OutputReg(disinstr.Memory.Rb);
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*pBuf++ = ')';
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break;
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case RS_FUNC:
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case RC_FUNC:
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case RPCC_FUNC:
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// one operand, in Ra
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.Memory.Ra);
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break;
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case MB_FUNC:
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case WMB_FUNC:
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case MB2_FUNC:
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case MB3_FUNC:
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case TRAPB_FUNC:
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case EXCB_FUNC:
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// no operands
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break;
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default:
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printf("we shouldn't get here \n");
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break;
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}
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break;
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case ALPHA_JUMP:
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OutputString(findFuncName(pEntry, disinstr.Jump.Function));
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.Jump.Ra);
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*pBuf++ = ',';
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*pBuf++ = '(';
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OutputReg(disinstr.Jump.Rb);
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*pBuf++ = ')';
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*pBuf++ = ',';
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OutputHex(disinstr.Jump.Hint, (WIDTH_HINT + 3)/4, TRUE);
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Ea = (ULONG)GetRegValue(GetIntRegNumber(disinstr.Jump.Rb)) & (~3);
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OutputEffectiveAddress(Ea);
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break;
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case ALPHA_BRANCH:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.Branch.Ra);
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*pBuf++ = ',';
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//
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// The next line might be a call to GetNextOffset, but
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// GetNextOffset assumes that it should work from REGFIR.
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//
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Ea = Flat(*poffset) +
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sizeof(ulong) +
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(disinstr.Branch.BranchDisp * 4);
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OutputHex(Ea, 8, FALSE);
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OutputEffectiveAddress(Ea);
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break;
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case ALPHA_FP_BRANCH:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputFReg(disinstr.Branch.Ra);
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*pBuf++ = ',';
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//
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// The next line might be a call to GetNextOffset, but
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// GetNextOffset assumes that it should work from REGFIR.
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//
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Ea = Flat(*poffset) +
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sizeof(ulong) +
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(disinstr.Branch.BranchDisp * 4);
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OutputHex(Ea, 8, FALSE);
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OutputEffectiveAddress(Ea);
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break;
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case ALPHA_OPERATE:
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OutputString(findFuncName(pEntry, disinstr.OpReg.Function));
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.OpReg.Ra);
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*pBuf++ = ',';
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if (disinstr.OpReg.RbvType) {
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*pBuf++ = '#';
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OutputHex(disinstr.OpLit.Literal, (WIDTH_LIT + 3)/4, TRUE);
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} else
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OutputReg(disinstr.OpReg.Rb);
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*pBuf++ = ',';
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OutputReg(disinstr.OpReg.Rc);
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break;
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case ALPHA_FP_OPERATE:
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{
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ULONG Function;
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ULONG Flags;
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Flags = disinstr.FpOp.Function & MSK_FP_FLAGS;
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Function = disinstr.FpOp.Function & MSK_FP_OP;
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#if 0
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if (fVerboseOutput) {
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dprintf("In FP_OPERATE: Flags %08x Function %08x\n",
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Flags, Function);
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dprintf("opcode %d \n", opcode);
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}
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#endif
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//
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// CVTST and CVTST/S are different: they look like
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// CVTTS with some flags set
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//
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if (Function == CVTTS_FUNC) {
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if (disinstr.FpOp.Function == CVTST_S_FUNC) {
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Function = CVTST_S_FUNC;
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Flags = NONE_FLAGS;
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}
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if (disinstr.FpOp.Function == CVTST_FUNC) {
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Function = CVTST_FUNC;
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Flags = NONE_FLAGS;
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}
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}
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OutputString(findFuncName(pEntry, Function));
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//
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// Append the opcode qualifier, if any, to the opcode name.
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//
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if ( (opcode == IEEEFP_OP) || (opcode == VAXFP_OP)
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|| (Function == CVTQL_FUNC) ) {
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OutputString(findFlagName(Flags, Function));
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}
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BlankFill(OPRNDCOL);
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//
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// If this is a convert instruction, only Rb and Rc are used
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//
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if (strncmp("cvt", findFuncName(pEntry, Function), 3) != 0) {
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OutputFReg(disinstr.FpOp.Fa);
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*pBuf++ = ',';
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}
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OutputFReg(disinstr.FpOp.Fb);
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*pBuf++ = ',';
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OutputFReg(disinstr.FpOp.Fc);
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break;
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}
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case ALPHA_FP_CONVERT:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputFReg(disinstr.FpOp.Fa);
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*pBuf++ = ',';
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OutputFReg(disinstr.FpOp.Fb);
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break;
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case ALPHA_CALLPAL:
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OutputString(findFuncName(pEntry, disinstr.Pal.Function));
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break;
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case ALPHA_EV4_PR:
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if ((disinstr.Long & MSK_EV4_PR) == 0)
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OutputString("NOP");
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else {
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.EV4_PR.Ra);
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*pBuf++ = ',';
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if(disinstr.EV4_PR.Ra != disinstr.EV4_PR.Rb) {
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OutputReg(disinstr.EV4_PR.Rb);
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*pBuf++ = ',';
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};
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OutputString(findFuncName(pEntry, (disinstr.Long & MSK_EV4_PR)));
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};
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break;
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case ALPHA_EV4_MEM:
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OutputString(pEntry->pszAlphaName);
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BlankFill(OPRNDCOL);
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OutputReg(disinstr.EV4_MEM.Ra);
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*pBuf++ = ',';
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OutputReg(disinstr.EV4_MEM.Rb);
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break;
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case ALPHA_EV4_REI:
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OutputString(pEntry->pszAlphaName);
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break;
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default:
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OutputString("Invalid type");
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break;
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};
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Off(*poffset) += sizeof(ULONG);
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NotFlat(*poffset);
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ComputeFlatAddress(poffset, NULL);
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*pBuf++ = '\n';
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*pBuf = '\0';
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return(TRUE);
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}
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/* BlankFill - blank-fill buffer
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*
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* Purpose:
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* To fill the buffer at *pBuf with blanks until
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* position count is reached.
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*
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* Input:
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* None.
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*
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* Output:
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* None.
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*
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***********************************************************************/
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void BlankFill(ULONG count)
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{
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do
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*pBuf++ = ' ';
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while (pBuf < pBufStart + count);
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}
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/* OutputHex - output hex value
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*
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* Purpose:
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* Output the value in outvalue into the buffer
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* pointed by *pBuf. The value may be signed
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* or unsigned depending on the value fSigned.
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*
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* Input:
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* outvalue - value to output
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* length - length in digits
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* fSigned - TRUE if signed else FALSE
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*
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* Output:
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* None.
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*
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***********************************************************************/
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UCHAR HexDigit[16] = {
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'0', '1', '2', '3', '4', '5', '6', '7',
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'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'
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};
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void OutputHex (ULONG outvalue, ULONG length, BOOLEAN fSigned)
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{
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UCHAR digit[8];
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LONG index = 0;
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if (fSigned && (LONG)outvalue < 0) {
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*pBuf++ = '-';
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outvalue = - (LONG)outvalue;
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}
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do {
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digit[index++] = HexDigit[outvalue & 0xf];
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outvalue >>= 4;
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}
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while ((fSigned && outvalue) || (!fSigned && index < (LONG)length));
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while (--index >= 0)
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*pBuf++ = digit[index];
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}
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/*** OutputDisSymbol - output symbol for disassembly
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*
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* Purpose:
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* Access symbol table with given offset and put string into buffer.
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*
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* Input:
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* offset - offset of address to output
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*
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* Output:
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* buffer pointed by pBuf updated with string:
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* if symbol, no disp: <symbol>(<offset>)
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* if symbol, disp: <symbol>+<disp>(<offset>)
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* if no symbol, no disp: <offset>
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*
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*************************************************************************/
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/* OutputString - output string
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*
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* Purpose:
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* Copy the string into the buffer pointed by pBuf.
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*
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* Input:
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* *pStr - pointer to string
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*
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* Output:
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* None.
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*
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***********************************************************************/
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void OutputString (char *pStr)
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{
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while (*pStr)
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*pBuf++ = *pStr++;
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}
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void OutputReg (ULONG regnum)
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{
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OutputString(pszReg[GetIntRegNumber(regnum)]);
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}
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void OutputFReg (ULONG regnum)
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{
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*pBuf++ = 'f';
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if (regnum > 9)
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*pBuf++ = (UCHAR)('0' + regnum / 10);
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*pBuf++ = (UCHAR)('0' + regnum % 10);
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}
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/*** OutputEffectiveAddress - Print EA symbolically
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*
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* Purpose:
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* Given the effective address (for a branch, jump or
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* memory instruction, print it symbolically, if
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* symbols are available.
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*
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* Input:
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* offset - computed by the caller as
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* for jumps, the value in Rb
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* for branches, func(PC, displacement)
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* for memory, func(PC, displacement)
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*
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* Returns:
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* None
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*
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*************************************************************************/
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void OutputEffectiveAddress(ULONG offset)
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{
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UCHAR chAddrBuffer[SYMBOLSIZE];
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ULONG displacement;
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PUCHAR pszTemp;
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UCHAR ch;
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//
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// MBH - i386 compiler bug with fast calling standard.
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// If "chAddrBuffer is used as a calling argument to
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// GetSymbol, it believes (here, but not in the other
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// uses of GetSymbol that the size is 60+8=68.
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//
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PUCHAR pch = chAddrBuffer;
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BlankFill(EACOL);
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GetSymbolStdCall(offset, pch, &displacement, NULL);
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if (chAddrBuffer[0]) {
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pszTemp = chAddrBuffer;
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while (ch = *pszTemp++)
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*pBuf++ = ch;
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if (displacement) {
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*pBuf++ = '+';
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OutputHex(displacement, 8, TRUE);
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}
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}
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else {
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OutputHex(offset, 8, FALSE);
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}
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}
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/*** GetNextOffset - compute offset for trace or step
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*
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* Purpose:
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* From a limited disassembly of the instruction pointed
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* by the FIR register, compute the offset of the next
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* instruction for either a trace or step operation.
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*
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* trace -> the next instruction to execute
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* step -> the instruction in the next memory location or the
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* next instruction executed due to a branch (step over
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* subroutine calls).
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*
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* Input:
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* result - where to put the next offset as an ADDR
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* fStep - TRUE for step offset; FALSE for trace offset
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*
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* Returns:
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* step or trace offset if input is TRUE or FALSE, respectively
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* in result
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*
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*************************************************************************/
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void
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GetNextOffset (PADDR result, BOOLEAN fStep)
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{
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ULONG rv;
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ULONG opcode;
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ULONG firaddr;
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ULONG updatedpc;
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ULONG branchTarget;
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ADDR fir;
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// Canonical form to shorten tests; Abs is absolute value
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LONG Can, Abs;
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CONVERTED_DOUBLE Rav;
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CONVERTED_DOUBLE Fav;
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CONVERTED_DOUBLE Rbv;
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//
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// Get current address
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//
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firaddr = (ULONG)GetRegValue(REGFIR);
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//
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// relative addressing updates PC first
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// Assume next sequential instruction is next offset
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//
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updatedpc = firaddr + sizeof(ULONG);
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rv = updatedpc;
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ADDR32( &fir, firaddr);
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GetMemDword(&fir, &(disinstr.Long)); // Get current instruction
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opcode = disinstr.Memory.Opcode;
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switch(findOpCodeEntry(opcode)->iType) {
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case ALPHA_JUMP:
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switch(disinstr.Jump.Function) {
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case JSR_FUNC:
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case JSR_CO_FUNC:
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if (fStep) {
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//
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// Step over the subroutine call;
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//
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break;
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}
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//
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// fall through
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//
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case JMP_FUNC:
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case RET_FUNC:
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Rbv.li.QuadPart = GetRegValue( GetIntRegNumber(disinstr.Jump.Rb) );
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rv = (Rbv.li.LowPart & (~3));
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break;
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}
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break;
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case ALPHA_BRANCH:
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branchTarget = (updatedpc + (disinstr.Branch.BranchDisp * 4));
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Rav.li.QuadPart = GetRegValue(GetIntRegNumber(disinstr.Branch.Ra));
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//
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// set up a canonical value for computing the branch test
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// - works with ALPHA, MIPS and 386 hosts
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//
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|
||
Can = Rav.li.LowPart & 1;
|
||
|
||
if ((LONG)Rav.li.HighPart < 0) {
|
||
Can |= 0x80000000;
|
||
}
|
||
|
||
if ((Rav.li.LowPart & 0xfffffffe) || (Rav.li.HighPart & 0x7fffffff)) {
|
||
Can |= 2;
|
||
}
|
||
|
||
#if 0
|
||
if (fVerboseOutput) {
|
||
dprintf("Rav High %08lx Low %08lx Canonical %08lx\n",
|
||
Rav.li.HighPart, Rav.li.LowPart, Can);
|
||
dprintf("returnvalue %08lx branchTarget %08lx\n",
|
||
rv, branchTarget);
|
||
}
|
||
#endif
|
||
|
||
switch(opcode) {
|
||
case BR_OP: rv = branchTarget; break;
|
||
case BSR_OP: if (!fStep) rv = branchTarget; break;
|
||
case BEQ_OP: if (Can == 0) rv = branchTarget; break;
|
||
case BLT_OP: if (Can < 0) rv = branchTarget; break;
|
||
case BLE_OP: if (Can <= 0) rv = branchTarget; break;
|
||
case BNE_OP: if (Can != 0) rv = branchTarget; break;
|
||
case BGE_OP: if (Can >= 0) rv = branchTarget; break;
|
||
case BGT_OP: if (Can > 0) rv = branchTarget; break;
|
||
case BLBC_OP: if ((Can & 0x1) == 0) rv = branchTarget; break;
|
||
case BLBS_OP: if ((Can & 0x1) == 1) rv = branchTarget; break;
|
||
};
|
||
|
||
break;
|
||
|
||
|
||
case ALPHA_FP_BRANCH:
|
||
|
||
branchTarget = (updatedpc + (disinstr.Branch.BranchDisp * 4));
|
||
|
||
GetFloatingPointRegValue(disinstr.Branch.Ra, &Fav);
|
||
|
||
//
|
||
// Set up a canonical value for computing the branch test
|
||
//
|
||
|
||
Can = Fav.li.HighPart & 0x80000000;
|
||
|
||
//
|
||
// The absolute value is needed -0 and non-zero computation
|
||
//
|
||
|
||
Abs = Fav.li.LowPart || (Fav.li.HighPart & 0x7fffffff);
|
||
|
||
if (Can && (Abs == 0x0)) {
|
||
|
||
//
|
||
// negative 0 should be considered as zero
|
||
//
|
||
|
||
Can = 0x0;
|
||
|
||
} else {
|
||
|
||
Can |= Abs;
|
||
|
||
}
|
||
|
||
#if 0
|
||
if (fVerboseOutput) {
|
||
dprintf("Fav High %08lx Low %08lx Canonical %08lx Absolute %08lx\n",
|
||
Fav.li.HighPart, Fav.li.LowPart, Can, Abs);
|
||
dprintf("returnvalue %08lx branchTarget %08lx\n",
|
||
rv, branchTarget);
|
||
}
|
||
#endif
|
||
|
||
switch(opcode) {
|
||
case FBEQ_OP: if (Can == 0) rv = branchTarget; break;
|
||
case FBLT_OP: if (Can < 0) rv = branchTarget; break;
|
||
case FBNE_OP: if (Can != 0) rv = branchTarget; break;
|
||
case FBLE_OP: if (Can <= 0) rv = branchTarget; break;
|
||
case FBGE_OP: if (Can >= 0) rv = branchTarget; break;
|
||
case FBGT_OP: if (Can > 0) rv = branchTarget; break;
|
||
};
|
||
|
||
break;
|
||
};
|
||
|
||
#if 0
|
||
if (fVerboseOutput) {
|
||
dprintf("GetNextOffset returning %08lx\n", rv);
|
||
}
|
||
#endif
|
||
|
||
ADDR32( result, rv );
|
||
}
|
||
|
||
/*** fDelayInstruction - returns flag TRUE if delayed instruction
|
||
*
|
||
* Purpose:
|
||
* From a limited disassembly of the instruction pointed
|
||
* by the FIR register, return TRUE if delayed, else FALSE.
|
||
*
|
||
* Input:
|
||
* None.
|
||
*
|
||
* Returns:
|
||
* On Alpha, this always returns FALSE.
|
||
*
|
||
*************************************************************************/
|
||
|
||
BOOLEAN fDelayInstruction (void)
|
||
{
|
||
return(FALSE);
|
||
}
|
||
|