140 lines
4.1 KiB
ArmAsm
140 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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*
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* $RCSfile: pxcache.s $
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* $Revision: 1.7 $
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* $Date: 1996/01/11 07:54:50 $
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* $Locker: $
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*
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* Derived from:
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* Source: halfire/ppc/pxcache.s
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* Revision: 1.6
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* Date: 1995/04/17 21:17:37
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*/
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//++
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//
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// Copyright (c) 1993, 1994, 1995 IBM Corporation
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//
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// Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// pxcache.s
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//
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// Abstract:
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//
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// This module implements the routines to flush cache on the PowerPC.
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//
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// Author:
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//
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// Peter L. Johnston (plj@vnet.ibm.com) September 1993
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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// 27-Dec-93 plj Added 603 support.
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// 13-Mar-94 plj Fixed problem introduced during switch to pas,
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// added 604 support.
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// 18-Jan-95 plj Add 603+, 604+ and 620 support.
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//
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//--
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#include "kxppc.h"
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//++
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//
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// HalpSweepPhysicalRangeInBothCaches
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//
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// Force data in a given PHYSICAL address range to memory and
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// invalidate from the block in the instruction cache.
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//
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// This implementation assumes a block size of 32 bytes. It
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// will still work on the 620.
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//
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// Arguments:
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//
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// r.3 Start physical PAGE number.
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// r.4 Starting offset within page. Cache block ALIGNED.
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// r.5 Length (in bytes)
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//
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// Return Value:
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//
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// None.
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//
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//--
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.set PAGE_SHIFT, 12
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LEAF_ENTRY(HalpSweepPhysicalRangeInBothCaches)
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//
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// Starting physical address = (PageNumber << PAGE_SHIFT) | Offset
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//
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rlwimi r.4, r.3, PAGE_SHIFT, 0xfffff000
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addi r.5, r.5, 31 // bump length by block size - 1
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srwi r.5, r.5, 5 // get number of blocks
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mflr r.0 // save return address
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mtctr r.5 // set loop count
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//
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// Interrupts MUST be disabled for the duration of this function as
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// we use srr0 and srr1 which will be destroyed by any exception or
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// interrupt.
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//
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DISABLE_INTERRUPTS(r.12,r.11) // r.11 <- disabled MSR
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// r.12 <- previous MSR
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//
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// Find ourselves in memory. This is needed as we must disable
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// both instruction and data translation. We do this while
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// interrupts are disabled only to try to avoid changing the
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// Link Register when an unwind might/could occur.
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//
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// The HAL is known to be in KSEG0 so its physical address is
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// its effective address with the top bit stripped off.
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//
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bl hspribc
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hspribc:
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mflr r.6 // r.6 <- &hspribc
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rlwinm r.6, r.6, 0, 0x7fffffff // r.6 &= 0x7fffffff
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addi r.6, r.6, hspribc.real - hspribc
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// r.6 = real &hspribc.real
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sync // ensure all previous loads and
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// stores are complete.
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mtsrr0 r.6 // address in real space
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rlwinm r.11, r.11, 0, ~0x30 // turn off Data and Instr relocation
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mtsrr1 r.11
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rfi // leap to next instruction
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hspribc.real:
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mtsrr0 r.0 // set return address
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mtsrr1 r.12 // set old MSR value
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hspribc.loop:
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// XXX dcbst 0, r.4 // flush data block to memory
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dcbf 0, r.4 // flush data block to memory
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icbi 0, r.4 // invalidate i-cache
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addi r.4, r.4, 32 // point to next block
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bdnz hspribc.loop // jif more to do
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sync // ensure all translations complete
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isync // don't even *think* about getting
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// ahead.
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rfi // return to caller and translated
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// mode
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DUMMY_EXIT(HalpSweepPhysicalRangeInBothCaches)
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