297 lines
7.2 KiB
C
297 lines
7.2 KiB
C
/*++
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Copyright (c) 1992 Silicon Graphics Incorparated
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Module Name:
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hardware.h
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Abstract:
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This include file defines all constants and types for
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the MIPS sound hardware.
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Author:
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Robin Speed (RobinSp) Created 14-Mar-92
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Revision History:
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Sameer Dekate (sameer@mips.com) 19-Aug-1992
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-Changes to support the MIPS sound board
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--*/
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#define INTERRUPT_MODE LevelSensitive
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#define IRQ_SHARABLE TRUE
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#define DMA_CHANNEL_BASE 2 // DMA channel no
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#define DMA_CHANNEL_A 0
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#define DMA_CHANNEL_B 1
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//
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// Define Sound Controller register structure.
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//
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typedef struct _SOUND_REGISTERS {
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volatile UCHAR DmaControl;
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volatile UCHAR Config;
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volatile UCHAR Endian;
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volatile UCHAR Reserved0;
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volatile UCHAR RightInControl;
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volatile UCHAR LeftInControl;
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volatile UCHAR RightOutControl;
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volatile UCHAR LeftOutControl;
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volatile UCHAR Reserved1;
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volatile UCHAR Revision;
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volatile UCHAR Reserved2;
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volatile UCHAR ParallelPort;
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volatile UCHAR Test;
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volatile UCHAR SerialControl;
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volatile UCHAR DataFormat;
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volatile UCHAR Status;
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} SOUND_REGISTERS, *PSOUND_REGISTERS;
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typedef struct _SOUND_HARDWARE {
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PSOUND_REGISTERS SoundVirtualBase;
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ULONG TcInterruptsPending;
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} SOUND_HARDWARE, PSOUND_HARDWARE;
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//
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// Defines for DMA Control Register
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//
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#define REC_CHANNEL_IN_USE 0xC0
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#define PLAY_CHANNEL_IN_USE 0x30
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#define DATA_CONTROL 0x08
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#define DCB 0x04
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#define REC_ENABLE 0x02
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#define PLAY_ENABLE 0x01
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#define REC_CHANNEL_SHIFT 6
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#define PLAY_CHANNEL_SHIFT 4
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#define CH5_IN_USE 0x3
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#define CH4_IN_USE 0x2
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#define CH3_IN_USE 0x1
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#define CH2_IN_USE 0x0
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//
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// Defines for Configuration Register
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//
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#define PLAY_XLATION 0xC0
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#define REC_XLATION 0x30
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#define PLAY_8WAVE_ENABLE 0x08
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#define REC_8WAVE_ENABLE 0x04
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#define REC_OVF_INTR 0x02
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#define PLAY_UND_INTR 0x01
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#define PLAY_XLATION_SHIFT 6
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#define REC_XLATION_SHIFT 4
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#define MONO_8BIT 0x3
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#define MONO_16BIT 0x2
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#define STEREO_8BIT 0x1
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#define STEREO_16BIT 0x0
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#define CR_MONO 0x2
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#define CR_STEREO 0x0
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#define CR_8BIT 0x1
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#define CR_16BIT 0x0
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//
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// Defines for Endian Register
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//
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#define DMA_TCINTR_ENABLE 0x04
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#define DMA_TCINTR 0x02
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#define BIG_ENDIAN 0x01
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//
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// Defines for Right In Control Register
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//
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#define MON_ATTN_MASK 0xF0
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#define RIGHT_INPUT_GAIN_MASK 0x0F
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#define MON_ATTN_SHIFT 4
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//
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// Defines for Left In Control Register
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//
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#define PARALLELIO_MASK 0xC0
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#define OVR_RANGE 0x20
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#define MIC_LEVEL_INPUT 0x10
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#define LINE_LEVEL_INPUT 0x00
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#define PARALLELIO_CDROM 0x00
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#define PARALLELIO_LINEIN 0x40
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#define MICROPHONE_ENABLE MIC_LEVEL_INPUT
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#define LINEIN_ENABLE (LINE_LEVEL_INPUT | PARALLELIO_LINEIN)
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#define CDROM_ENABLE (LINE_LEVEL_INPUT | PARALLELIO_CDROM)
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// used for selection ( in snd.c)
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#define MICROPHONE_SELECT 0
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#define LINEIN_SELECT 1
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#define CDROM_SELECT 2
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#define LEFT_INPUT_GAIN_MASK 0x0F
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//
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// Defines for Right Out Control Register
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//
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#define SPEAKER_ENABLE 0x40
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#define RIGHT_OUTPUT_ATTN_MASK 0x3F
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//
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// Defines for Left Out Control Register
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//
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#define HEADPHONE_ENABLE 0x80
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#define LINEOUT_ENABLE 0x40
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#define LEFT_OUTPUT_ATTN_MASK 0x3F
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//
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// Defines for Revision Register
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//
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#define REVISION 0x0F
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//
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// Defines for Parallel Port
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//
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#define PARALLEL_IO 0xC0
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//
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// Defines for Test Register
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//
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#define ADL_LOOPBACKMODE 0x02
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#define LOOPBACKTEST_ENABLE 0x01
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//
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// Defines for Serial Control Register
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//
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#define CLOCK_SOURCE_SELECT 0x30
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#define FRAME_SIZE_SELECT 0x0C // Hardwired to 64bits per frame
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#define XMIT_CLOCK_SOURCE 0x02 // Generate SCLK and FSYNC
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#define XTAL1 0x10 // 24.576MHz clock source
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#define XTAL2 0x20 // 16.9344MHz clock source
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#define XMIT_ENABLE 0x01
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//
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// Defines for Data Format Register
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//
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#define DATA_CONVERSION_FREQ 0x38
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#define STEREO 0x04
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#define DATA_FORMAT_SELECT 0x03
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// data format values ; its same for both 8bit and 16bit formats
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#define LINEAR_16BIT 0x00
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#define M_LAW_8BIT 0x01
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#define A_LAW_8BIT 0x02
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//
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// Defines for Status Register
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//
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#define DATA_CTRL_HNDSHAKE 0x04
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//
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// Define Frequency values.
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//
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// 8 Khz Sampling Frequency
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#define CLKSRC_8KHZ XTAL1 // Choose XTAL1 for 8KHz in serial reg
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#define CONFREQ_8KHZ 0x00 // Data format register DFR[2..0]
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// 11 Khz Sampling Frequency
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#define CLKSRC_11KHZ XTAL2 // Choose XTAL2 for 11KHz in serial reg
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#define CONFREQ_11KHZ 0x08 // Data format register DFR[2..0]
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// 22 Khz Sampling Frequency
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#define CLKSRC_22KHZ XTAL2 // Choose XTAL2 for 22KHz in serial reg
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#define CONFREQ_22KHZ 0x18 // Data format register DFR[2..0]
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// 44 Khz Sampling Frequency
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#define CLKSRC_44KHZ XTAL2 // Choose XTAL2 for 44KHz in serial reg
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#define CONFREQ_44KHZ 0x28 // Data format register DFR[2..0]
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#define SOUND_11KHZ 0x0
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#define SOUND_22KHZ 0x1
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#define SOUND_44KHZ 0x2
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#define SOUND_DISABLE 0x3
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//
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// Define Resolution values.
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//
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#define SOUND_8BITS 0x0
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#define SOUND_16BITS 0x1
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//
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// Define NumberOfChannels values.
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//
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#define SOUND_MONO 0x0
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#define SOUND_STEREO 0x1
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//
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// Defaults
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//
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#define WAVE_INPUT_DEFAULT_RATE 11025 // Samples per second
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#define WAVE_OUTPUT_DEFAULT_RATE 11025 // Samples per second
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// The audio board in it present design gives incorrect values when byte
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// accesses at odd addresses are done. The way to get around it is to access
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// bytes at odd addresses, using half-word accesses at the even address which
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// is immediately below it, and taking the most significant byte of the half
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// word. The above is true only for read accesses. There are no problems for
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// write accesses.
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#define READ_ODD_REG(x) ((READ_REGISTER_USHORT(x - 1) & 0xFF00) >> 8)
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#define READAUDIO_DMACNTRL(x) READ_REGISTER_UCHAR(x->DmaControl)
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#define READAUDIO_CONFIG(x) READ_ODD_REG(x->Config)
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#define READAUDIO_ENDIAN(x) READ_REGISTER_UCHAR(x->Endian)
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#define READAUDIO_RICNTRL(x) READ_REGISTER_UCHAR(x->RightInControl)
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#define READAUDIO_LICNTRL(x) READ_ODD_REG(x->LeftInControl)
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#define READAUDIO_ROCNTRL(x) READ_REGISTER_UCHAR(x->RightOutControl)
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#define READAUDIO_LOCNTRL(x) READ_ODD_REG(x->LeftOutControl)
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#define READAUDIO_REVISION(x) READ_ODD_REG(x->Revision);
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#define READAUDIO_PPORT(x) READ_ODD_REG(x->ParallelPort)
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#define READAUDIO_TEST(x) READ_REGISTER_UCHAR(x->Test)
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#define READAUDIO_SCNTRL(x) READ_ODD_REG(x->SerialControl)
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#define READAUDIO_DATAFMT(x) READ_REGISTER_UCHAR(x->DataFormat)
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#define READAUDIO_STATUS(x) READ_ODD_REG(x->Status)
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#define WRITEAUDIO_DMACNTRL(x,y) WRITE_REGISTER_UCHAR(x->DmaControl,y)
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#define WRITEAUDIO_CONFIG(x,y) WRITE_REGISTER_UCHAR(x->Config,y)
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#define WRITEAUDIO_ENDIAN(x,y) WRITE_REGISTER_UCHAR(x->Endian,y)
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#define WRITEAUDIO_RICNTRL(x,y) WRITE_REGISTER_UCHAR(x->RightInControl,y)
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#define WRITEAUDIO_LICNTRL(x,y) WRITE_REGISTER_UCHAR(x->LeftInControl,y)
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#define WRITEAUDIO_ROCNTRL(x,y) WRITE_REGISTER_UCHAR(x->RightOutControl,y)
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#define WRITEAUDIO_LOCNTRL(x,y) WRITE_REGISTER_UCHAR(x->LeftOutControl,y)
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#define WRITEAUDIO_REVISION(x,y) WRITE_REGISTER_UCHAR(x->Revision,y)
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#define WRITEAUDIO_PPORT(x,y) WRITE_REGISTER_UCHAR(x->ParallelPort,y)
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#define WRITEAUDIO_TEST(x,y) WRITE_REGISTER_UCHAR(x->Test,y)
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#define WRITEAUDIO_SCNTRL(x,y) WRITE_REGISTER_UCHAR(x->SerialControl,y)
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#define WRITEAUDIO_DATAFMT(x,y) WRITE_REGISTER_UCHAR(x->DataFormat,y)
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#define WRITEAUDIO_STATUS(x,y) WRITE_REGISTER_UCHAR(x->Status,y)
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