271 lines
7.2 KiB
C
271 lines
7.2 KiB
C
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/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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174x.h
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Abstract:
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This module contains the structures, specific to the Adaptec 174x
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host bus adapter, used by the SCSI port driver. Data structures
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that are part of standard ANSI SCSI will be defined in a header
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file that will be available to all SCSI device drivers.
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Author:
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Mike Glass
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Revision History:
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--*/
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#include "scsi.h"
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#define MAXIMUM_EISA_SLOTS 0x10
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#define EISA_ADDRESS_BASE 0x0C80
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#define MAXIMUM_SGL_DESCRIPTORS 0x11
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#define MAXIMUM_DESCRIPTOR_SIZE 0x3FFFFF
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#define MAXIMUM_TRANSFER_SIZE 0xFFFFFF
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#define REQUEST_SENSE_BUFFER_SIZE 0x18
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//***************
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// *
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// Status Block *
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// *
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//***************
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typedef struct _STATUS_BLOCK {
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USHORT StatusWord;
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UCHAR HaStatus;
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UCHAR TargetStatus;
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ULONG ResidualByteCount;
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ULONG ResidualAddress;
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USHORT AdditionalStatusLength;
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UCHAR RequestSenseLength;
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UCHAR Reserved0;
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ULONG Reserved1;
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ULONG Reserved2;
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USHORT Reserved3;
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UCHAR Cdb[6];
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} STATUS_BLOCK, *PSTATUS_BLOCK;
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//
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// Status Word Bit Values
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//
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#define SB_STATUS_NO_ERROR 0x0001
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#define SB_STATUS_DATA_UNDERRUN 0x0002
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#define SB_STATUS_HA_QUEUE_FULL 0x0008
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#define SB_STATUS_SPECIFICATION_CHECK 0x0010
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#define SB_STATUS_DATA_OVERRUN 0x0020
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#define SB_STATUS_CHAINING_HALTED 0x0040
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#define SB_STATUS_SCB_INTERRUPT 0x0080
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#define SB_STATUS_ADDITIONAL_STATUS 0x0100
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#define SB_STATUS_SENSE_INFORMATION 0x0200
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#define SB_STATUS_INIT_REQUIRED 0x0800
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#define SB_STATUS_MAJOR_ERROR 0x1000
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#define SB_STATUS_EXT_CONT_ALLEGIANCE 0x4000
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//
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// HOST_ADAPTER_STATUS
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//
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#define SB_HASTATUS_HOST_ABORTED 0x04
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#define SB_HASTATUS_ADAPTER_ABORTED 0x05
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#define SB_HASTATUS_FW_NOT_DOWNLOADED 0x08
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#define SB_HASTATUS_TARGET_NOT_USED 0x0A
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#define SB_HASTATUS_SELECTION_TIMEOUT 0x11
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#define SB_HASTATUS_DATA_OVERUNDER_RUN 0x12
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#define SB_HASTATUS_UNEXPECTED_BUS_FREE 0x13
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#define SB_HASTATUS_INVALID_BUS_PHASE 0x14
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#define SB_HASTATUS_INVALID_OPERATION 0x16
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#define SB_HASTATUS_INVALID_SCSI_LINK 0x17
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#define SB_HASTATUS_INVALID_ECB 0x18
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#define SB_HASTATUS_DUPLICATE_TARGET 0x19
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#define SB_HASTATUS_INVALID_SGL 0x1A
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#define SB_HASTATUS_REQUEST_SENSE_FAILED 0x1B
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#define SB_HASTATUS_TAGGED_QUEUE_REJECTED 0x1C
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#define SB_HASTATUS_ADAPTER_HARDWARE_ERROR 0x20
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#define SB_HASTATUS_TARGET_NO_RESPOND 0x21
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#define SB_HASTATUS_ADAPTER_RESET_BUS 0x22
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#define SB_HASTATUS_DEVICE_RESET_BUS 0x23
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#define SB_HASTATUS_CHECKSUM_FAILURE 0x80
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//
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// Target Status - See SCSI.H
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//
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//**********************
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// *
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// Scatter Gather List *
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// *
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//**********************
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typedef struct _SG_DESCRIPTOR {
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ULONG Address;
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ULONG Length;
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} SG_DESCRIPTOR, *PSG_DESCRIPTOR;
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typedef struct _SGL {
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SG_DESCRIPTOR Descriptor[MAXIMUM_SGL_DESCRIPTORS];
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} SGL, *PSGL;
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//**************************
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// *
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// Enhanced Control Block *
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// *
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//**************************
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typedef struct _ECB {
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USHORT Command;
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USHORT Flags[2];
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USHORT Reserved1;
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ULONG PhysicalSgl;
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ULONG SglLength;
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ULONG StatusBlockAddress;
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ULONG NextEcb;
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ULONG Reserved2;
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ULONG SenseInfoAddress;
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UCHAR SenseInfoLength;
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UCHAR CdbLength;
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USHORT DataCheckSum;
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UCHAR Cdb[12];
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PVOID SrbAddress;
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PSCSI_REQUEST_BLOCK AbortSrb;
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SGL Sgl;
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STATUS_BLOCK StatusBlock;
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} ECB, *PECB;
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//
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// Commands
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//
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#define ECB_COMMAND_NO_OPERATION 0x0000
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#define ECB_COMMAND_INITIATOR_COMMAND 0x0001
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#define ECB_COMMAND_RUN_DIAGNOSTICS 0x0005
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#define ECB_COMMAND_INITIALIZE_SCSI 0x0006
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#define ECB_COMMAND_READ_SENSE_INFO 0x0008
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#define ECB_COMMAND_DOWNLOAD_FIRMWARE 0x0009
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#define ECB_COMMAND_READ_INQUIRY_DATA 0x000A
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#define ECB_COMMAND_TARGET_COMMAND 0x0010
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//
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// Flag word 1
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//
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#define ECB_FLAGS_CHAIN_NO_ERROR 0x0001
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#define ECB_FLAGS_DISABLE_INTERRUPT 0x0080
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#define ECB_FLAGS_SUPPRESS_UNDERRUN 0x0400
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#define ECB_FLAGS_SCATTER_GATHER 0x1000
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#define ECB_FLAGS_DISABLE_STATUS_BLOCK 0x4000
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#define ECB_FLAGS_AUTO_REQUEST_SENSE 0x8000
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//
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// Flag word 2
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//
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#define ECB_FLAGS_SIMPLE_QUEUE_TAG 0x0008
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#define ECB_FLAGS_HEAD_QUEUE_TAG 0x0018
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#define ECB_FLAGS_ORDERED_QUEUE_TAG 0x0028
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#define ECB_FLAGS_NO_DISCONNECT 0x0040
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#define ECB_FLAGS_DATA_TRANSFER 0x0100
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#define ECB_FLAGS_READ 0x0300
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#define ECB_FLAGS_WRITE 0x0100
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#define ECB_FLAGS_SUPPRESS_TRANSFER 0x0400
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#define ECB_FLAGS_CALCULATE_CHECKSUM 0x0800
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#define ECB_FLAGS_ERROR_RECOVERY 0x4000
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//****************************
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// *
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// EISA Controller registers *
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// *
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//****************************
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typedef struct _EISA_CONTROLLER {
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UCHAR BoardId[4]; // zC80
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UCHAR EBControl; // zC84
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UCHAR Unused[0x3B]; // zC85
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UCHAR PortAddress; // zCC0
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UCHAR BiosAddress; // zCC1
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UCHAR Interrupt; // zCC2
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UCHAR ScsiId; // zCC3
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UCHAR DmaChannel; // zCC4
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UCHAR Reserved[11]; // zCC5
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ULONG MailBoxOut; // zCD0
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UCHAR Attention; // zCD4
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UCHAR Control; // zCD5
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UCHAR InterruptStatus; // zCD6
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UCHAR Status; // zCD7
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ULONG MailBoxIn; // zCD8
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UCHAR MoreStatus; // zCDC
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} EISA_CONTROLLER, *PEISA_CONTROLLER;
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//
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// PortAddress Register Definition
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//
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#define ENHANCED_INTERFACE_ENABLED 0x80
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//
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// Bios address mask.
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//
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#define BIOS_ADDRESS 0x0f
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#define BIOS_ENABLED 0x40
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#define BIOS_LENGTH 0x4000
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//
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// Attention Register Bit Definitions
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//
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#define IMMEDIATE_COMMAND 0x10
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#define START_ECB 0x40
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#define ABORT_ECB 0x50
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//
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// Control Register Bit Definitions
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//
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#define SET_HOST_READY 0x20
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#define CLEAR_INTERRUPT 0x40
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#define HARD_RESET 0x80
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//
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// Interrupt Status Register Bit Definitions
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//
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#define ECB_COMPLETE_SUCCESS 0x01
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#define ECB_COMPLETE_SUCCESS_RETRY 0x05
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#define ADAPTER_FAILURE 0x07
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#define IMMEDIATE_COMMAND_SUCCESS 0x0A
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#define ECB_COMPLETE_ERROR 0x0C
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#define ASYNCHRONOUS_EVENT_NOTIFICATION 0x0D
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#define IMMEDIATE_COMMAND_ERROR 0x0E
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//
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// Status Register Bit Definition
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//
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#define ADAPTER_BUSY 0x01
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#define INTERRUPT_PENDING 0x02
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#define MAILBOX_OUT_EMPTY 0x04
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//
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// Immediate commands
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//
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#define ECB_IMMEDIATE_RESET 0x00000080
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#define ECB_IMMEDIATE_RESUME 0x00000090
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//
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// Status2 Register Definition
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//
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#define HOST_READY 0x01
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