146 lines
6.2 KiB
C
146 lines
6.2 KiB
C
/* Copyright (C) 1991, 1992 by Always Technology Corporation.
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This module contains information proprietary to
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Always Technology Corporation, and is be treated as confidential.
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*/
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#ifndef __33C93_H__
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#define __33C93_H__
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#define WDOwnIDReg 0 /* (R/W) */
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#define WDCDBSizeReg 0 /* (R/W) */
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#define WDControlReg 1 /* (R/W) */
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#define WDTimeoutReg 2
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#define WDCDBReg 3
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#define WDTarLUNReg 0xf /* Write: Sets target LUN; Read: Target status */
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/* byte from Select-and-Transfer commands */
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#define WDPhaseReg 0x10 /* WD Current phase */
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#define WDSyncReg 0x11 /* Sync. xfer configuration */
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#define WDCountReg 0x12 /* Xfer count msb, mid and lsb follow */
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#define WDDestIDReg 0x15 /* Destination SCSI ID for Sel or Resel */
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#define WDSourceReg 0x16 /* Who selected us; enable sel/resel */
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#define WDStatusReg 0x17 /* WD Command status */
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#define WDCMDReg 0x18 /* WD COmmand code register */
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#define WDDataReg 0x19 /* WD Data xfer register */
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#define WDAuxStatReg 0x1f /* Indirect access to aux. status */
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/* Aux Status bits: */
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#define WD_DBR 0x1 /* Data buffer ready */
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#define WD_Parity 0x2 /* Parity error */
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#define WD_CIP 0x10 /* Command in progress */
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#define WD_Busy 0x20 /* Level II command in progress */
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#define CommandIGN 0x40 // Last command ignored
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#define IntPending 0x80 // Interrupt pending
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/* Own ID register */
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#define DefualtHostID 0x7 /* Own SCSI ID */
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#define EnADV 0x8 /* Enable advanced features */
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#define EnHParity 0x10 /* Enable host parity */
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#define FreqSel 0xc0 /* Input frequency select */
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/* Western Digital control register */
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#define HaltPE 0x1 /* Halt on parity error */
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#define HaltATN 0x2 /* Halt on attention */
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#define EnableIDI 0x4 /* enable intermediate disc. inter. */
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#define EnableEDI 0x8 /* Enable ending disconnect inter. */
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#define EnableHHP 0x10 /* Enable halt on host parity */
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#define DMAModeMask 0xe0 /* DMA Mode select */
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#define DMAPIO 0x00 /* DMA mode: Polled I/O */
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#define DMABurst 0x20 /* DMA mode: Burst DMA */
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#define DMABus 0x40 /* DMA mode: 33C93 BUS mode */
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#define DMAStd 0x80 /* DMA mode: standard async. handshake */
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/* Target LUN register */
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#define WDTargetLUNMask 0x7 /* LUN of target */
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#define DisconOK 0x40 /* Allow disconnects */
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#define Valid 0x80 /* LUN fieldis valid */
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/* Destination ID register */
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#define DestID 0x7 /* Destination ID */
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#define DataReadDir 0x40 /* Data phase direction 1=Read */
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#define EnableSCC 0x80 /* Enable selct command chain */
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/* Source ID register */
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#define SourceID 0x7 /* Source ID */
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#define IDValid 0x8 /* Source ID valid */
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#define DisSelPar 0x20 /* Disable sel/resel parity */
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#define EnableSel 0x40 /* Enable selection */
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#define EnableRSel 0x80 /* Enable reselection */
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/* WD Status, read from registr 0x17 */
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//#define SubCode 0xf /* WD Status code */
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//#define StatusCode 0xf0 /* WD Status */
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#define WD_STAT_RESET 0x00 /* Reset received */
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#define WD_STAT_RESETA 0x01 /* Reset in advanced mode */
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#define WD_STAT_RESEL_OK 0x10 /* Reselct command OK */
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#define WD_STAT_SELECT_CMPLT 0x11 // Select command completed successfully
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#define WD_STAT_SandT_CMPLT 0x16 // Select and xfer completed OK
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#define WD_STAT_XFER_PAUSED 0x20
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#define WD_STAT_BAD_DISC 0x41 // Unexpected disconnect (bus free)
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#define WD_STAT_SEL_TO 0x42 // Selection timeout
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#define WD_STAT_PARITY 0x43 // A parity error caused the xfer to terminate, no atn
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#define WD_STAT_PARITY_ATN 0x44 // A parity error caused the xfer to terminate, atn asserted
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#define WD_STAT_SAVE_PTR 0x21 // A save data pointers during a S & T
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#define WD_STAT_BAD_STATUS 0x47 // An incorrect status byte
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#define WD_STAT_RESELECTED 0x80 // A device has reselected us
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#define WD_STAT_RESELECTED_A 0x81 // Been reselected in advanced mode
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#define WD_STAT_SELECTED 0x82 // We have been selected
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#define WD_STAT_SELECTED_ATN 0x83 // "" with ATN
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#define WD_STAT_DISCONNECT 0x85 /* Disconnect occured */
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/* Masked phase bits, makes use of fact that phase changes always have the 0x08 bit set */
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#define WD_PHASE_MASK 0x0f /* Mask for new phase */
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#define WD_MDATA_OUT 0x08 /* Masked-- Data out phase */
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#define WD_MDATA_IN 0x09
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#define WD_MCOMMAND 0x0a
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#define WD_MSTATUS 0x0b
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#define WD_MMSG_OUT 0x0e
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#define WD_MMSG_IN 0x0f
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/* WD Commands 0x */
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/* Level I */
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#define WDResetCmd 0
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#define WDAbortCmd 1
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#define WDSetAtnCmd 2
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#define WDNegAckCmd 3
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#define WDDisconnectCmd 4
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#define WDStatCmpltCmd 0xd /* Send Status and Command complete */
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#define WDSetIDICmd 0xf
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/* Level II */
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#define WDReselCmd 5
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#define WDSelATNCmd 6 /* Select w/ATN */
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#define WDSelCmd 7 /* Select w/o ATN */
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#define WDSelATNXCmd 8 /* Select w/ATN and transfer */
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#define WDSelXCmd 9 /* Select and transfer */
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#define WDRselRcvCmd 0xa /* Reselect and receive */
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#define WDRselSndCmd 0xb /* Reselect and send data */
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#define WDWaitRcvCmd 0xc /* Wait for select and receive */
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#define WDSendDiscCmd 0xe /* Send discconect message */
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#define WDRcvCmdCmd 0x10 /* Receive command */
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#define WDRcvDataCmd 0x11 /* Receive data */
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#define WDRcvMsgCmd 0x12 /* Receive message out */
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#define WDRcvUnspecCmd 0x13 /* Receive unspecified data */
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#define WDSendStatCmd 0x14 /* Send status */
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#define WDSendDataCmd 0x15
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#define WDSendMsgINCmd 0x16 /* Send message in */
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#define WDSendUnspecCmd 0x17 /* Send unspecified info */
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#define WDXlateAddrCmd 0x18 /* Translate address */
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#define WDXferInfo 0x20 /* Transfer info */
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#define WDSingleByte 0x80 /* Single byte xfer mask for xfer commands */
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/* State bits for the state field in the wd33c93s struct:
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(see wd33c93s.h)
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*/
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#define WD_NO_STATE 0x00 /* Non-descript state */
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#define WD_BLOCK_XFER 0x01 /* Doing a block xfer */
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#define WD_COMPOUND_CMD 0x02 /* Using WD's compound command */
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#define WD_COMPOUND_CMPLT 0x04 // WD Command complete interrupt seen
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#endif /* __33C93_H__ */
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