149 lines
4.0 KiB
C
149 lines
4.0 KiB
C
//-----------------------------------------------------------------------
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//
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// FILE: n5380.h
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//
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// N5380 Definitions File
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//
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// Revisions:
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// 09-01-92 KJB First.
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// 01-12-93 KJB Changed reset time.
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// 03-02-93 KJB/JAP Added N5380WaitLastByteSent.
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// 03-09-93 KJB Changed Names of bits/register to be consistent with
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// n5380 manual.
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// 03-19-93 JAP Implemented condition build FAR and NEAR pointers
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// 03-25-93 JAP Fixed up prototype typedef inconsistencies
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//
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//-----------------------------------------------------------------------
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// scsi reset time in usec
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#define SCSI_RESET_TIME 1000000
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//
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// Define the scsi phases
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//
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#define PHASE_NULL 0
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#define PHASE_DATAOUT 0
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#define PHASE_DATAIN 1
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#define PHASE_COMMAND 2
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#define PHASE_STATUS 3
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#define PHASE_MSGOUT 6
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#define PHASE_MSGIN 7
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//
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// Define n5380 registers
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//
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// NOTE: The names of these registers are
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// made to correspond exactly with the L5380 manual
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// page 7 of Logic Devices Incorporated
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//
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#define N5380_CURRENT_DATA 0
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#define N5380_OUTPUT_DATA 0
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#define N5380_INITIATOR_COMMAND 1
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#define N5380_MODE 2
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#define N5380_TARGET_COMMAND 3
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#define N5380_CURRENT_STATUS 4
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#define N5380_ID_SELECT 4
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#define N5380_DMA_STATUS 5
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#define N5380_START_DMA_SEND 5
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#define N5380_INPUT_DATA 6
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#define N5380_START_TARGET_RECIEVE 6
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#define N5380_RESET_INTERRUPT 7
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#define N5380_START_INITIATOR_RECEIVE 7
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//
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// Define 5380 register bit assignments
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//
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// NOTE: The names of these bit assignments are
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// made to correspond exactly with the L5380 manual
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// page 7 of Logic Devices Incorporated
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//
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// Initiator Command
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#define IC_RST 0x80
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#define IC_ARBITRATION_IN_PROGRESS 0x40
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#define IC_LOST_ARBITRATION 0x20
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#define IC_ACK 0x10
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#define IC_BSY 0x8
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#define IC_SEL 0x4
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#define IC_ATN 0x2
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#define IC_DATA_BUS 0x1
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// Mode Register
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#define MR_BLOCK_MODE_DMA 0x80
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#define MR_TARGET_MODE 0x40
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#define MR_ENABLE_PARITY_CHECKING 0x20
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#define MR_ENABLE_PARITY_INTERRUPT 0x10
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#define MR_ENABLE_EODMA_INTERRUPT 0x8
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#define MR_MONITOR_BSY 0x4
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#define MR_DMA_MODE 0x2
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#define MR_ARBITRATE 0x1
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// Target Command Register
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#define TC_LAST_BYTE_SENT 0x80
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#define TC_REQ 0x8
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#define TC_MSG 0x4
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#define TC_CD 0x2
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#define TC_IO 0x1
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// Current SCSI Control Register
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#define CS_RST 0x80
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#define CS_BSY 0x40
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#define CS_REQ 0x20
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#define CS_MSG 0x10
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#define CS_CD 0x8
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#define CS_IO 0x4
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#define CS_SEL 0x2
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#define CS_PARITY 0x1
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// DMA Status Register
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#define DS_DMA_END 0x80
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#define DS_DMA_REQUEST 0x40
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#define DS_PARITY_ERROR 0x20
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#define DS_INTERRUPT_REQUEST 0x10
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#define DS_PHASE_MATCH 0x8
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#define DS_BUSY_ERROR 0x4
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#define DS_ATN 0x2
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#define DS_ACK 0x1
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//
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// Public Routines Definitions
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//
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#define N5380EnableInterrupt(g) \
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N5380PortSet(g,N5380_MODE,MR_DMA_MODE)
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//
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// Public Routines
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//
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BOOLEAN N5380Interrupt(PADAPTER_INFO g);
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VOID N5380DisableInterrupt(PADAPTER_INFO g);
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USHORT N5380ToggleAck(PADAPTER_INFO g, ULONG usec);
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USHORT N5380GetByte(PADAPTER_INFO g, ULONG usec, PUCHAR byte);
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USHORT N5380PutByte(PADAPTER_INFO g, ULONG usec, UCHAR byte);
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USHORT N5380GetPhase(PADAPTER_INFO g, PUCHAR phase);
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USHORT N5380SetPhase(PADAPTER_INFO g, UCHAR phase);
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USHORT N5380WaitNoRequest(PADAPTER_INFO g, ULONG usec);
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USHORT N5380WaitRequest(PADAPTER_INFO g, ULONG usec);
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USHORT N5380WaitNoBusy(PADAPTER_INFO g, ULONG usec);
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USHORT N5380WaitBusy(PADAPTER_INFO g, ULONG usec);
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USHORT N5380WaitLastByteSent(PADAPTER_INFO g, ULONG usec);
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USHORT N5380Select(PADAPTER_INFO g, UCHAR target, UCHAR lun);
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VOID N5380ResetBus(PADAPTER_INFO g);
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BOOLEAN N5380CheckAdapter(PADAPTER_INFO g);
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VOID N5380DebugDump(PADAPTER_INFO g);
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VOID N5380EnableDmaWrite(PADAPTER_INFO g);
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VOID N5380EnableDmaRead(PADAPTER_INFO g);
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VOID N5380DisableDmaRead(PADAPTER_INFO g);
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BOOLEAN N5380PortTest(PADAPTER_INFO g,UCHAR reg,UCHAR mask);
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VOID N5380PortClear(PADAPTER_INFO g,UCHAR reg,UCHAR byte);
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VOID N5380PortSet(PADAPTER_INFO g,UCHAR reg,UCHAR byte);
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VOID N5380DisableDmaWrite (PADAPTER_INFO g);
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