146 lines
3.9 KiB
C
146 lines
3.9 KiB
C
/*++
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Copyright (c) 1991 Microsoft Corporation
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Copyright (c) 1991 Compaq Computer Corporation
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Module Name:
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s3scsi.h
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Abstract:
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The module defines the structures, and defines for the 32-bit
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GIO bus HPC scsi interface.
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Author:
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Jeff Havens (jhavens) 20-June-1991
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Tom Bonola (o-tomb) 25-Aug-1991
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Revision History:
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--*/
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#ifndef _S3SCSI_
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#define _S3SCSI_
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#include "sgidef.h"
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//
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// Define the SCSI host adapter card register structure.
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//
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typedef struct _CARD_REGISTERS {
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UCHAR fill1;
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UCHAR InternalAddress; // SCSI.ADDR
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UCHAR fill2[3];
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UCHAR IoChannel; // SCSI.DATA
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UCHAR fill3[2];
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}CARD_REGISTERS, *PCARD_REGISTERS;
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//
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// Define the SCSI host adapter card control register structure.
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//
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typedef struct _CARD_CONTROL {
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UCHAR ResetScsiBus : 1;
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UCHAR EnableDmaWrite : 1;
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UCHAR SetBufferedIo : 1;
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UCHAR SetIrql : 3;
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UCHAR SetDmaRequest : 2;
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}CARD_CONTROL, *PCARD_CONTROL;
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//
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// Specify board dependent parameters.
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//
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#define CLOCK_CONVERSION_FACTOR CLOCK_20MHZ
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#define SYNCHRONOUS_OFFSET 0x0c
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#define SYNCHRONOUS_PERIOD 0x32
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#define SYNCHRONOUS_PERIOD_STEP 0x32
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#define ASYNCHRONOUS_OFFSET 0x00
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#define ASYNCHRONOUS_PERIOD 0X02
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#define SCSI_CLOCK_SPEED 20 // Clock speed of the WD protocol chip in MHz.
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#define SELECT_TIMEOUT_VALUE (SCSI_CLOCK_SPEED * 4) // = (Input clock * 250ms timeout) / 80 rounded up.
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#define CARD_DMA_MODE DMA_BURST
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//
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// SCSI Protocol Chip Control read and write macros.
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//
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#define SCSI_READ(ChipAddr, Register) ( \
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ScsiPortWritePortUchar(&((ChipAddr)->InternalAddress), \
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(UCHAR) &((PSCSI_REGISTERS) 0)->Register), \
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ScsiPortReadPortUchar(&((ChipAddr)->IoChannel)))
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#define SCSI_READ_AUX(ChipAddr, Register) \
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(ScsiPortReadPortUchar (&((ChipAddr)->InternalAddress)))
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#define SCSI_WRITE(ChipAddr, Register, Value) { \
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ScsiPortWritePortUchar(&((ChipAddr)->InternalAddress), \
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(UCHAR) &((PSCSI_REGISTERS) 0)->Register); \
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ScsiPortWritePortUchar(&((ChipAddr)->IoChannel), (Value)); }
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#define SCSI_READ_TRANSFER_COUNT(ChipAddr, Count) { \
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ScsiPortWritePortUchar(&((ChipAddr)->InternalAddress), \
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(UCHAR) &((PSCSI_REGISTERS) 0)->TransferCountMsb); \
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Count = ScsiPortReadPortUchar(&((ChipAddr)->IoChannel)) << 16; \
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Count |= ScsiPortReadPortUchar(&((ChipAddr)->IoChannel)) << 8 ; \
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Count |= ScsiPortReadPortUchar(&((ChipAddr)->IoChannel)); }
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#define SCSI_WRITE_TRANSFER_COUNT(ChipAddr, Count) { \
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SCSI_WRITE(ChipAddr, TransferCountMsb, Count >> 16); \
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ScsiPortWritePortUchar(&((ChipAddr)->IoChannel), Count >> 8); \
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ScsiPortWritePortUchar(&((ChipAddr)->IoChannel), Count); }
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#define SCSI_RESET_BUS(ChipAddr) \
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*(volatile ULONG *)&SCSI0_HPCREG->ScsiCNTL = SGI_CNTL_SCSIRESET; \
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KeStallExecutionProcessor( 25 ); \
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*(volatile ULONG *)&SCSI0_HPCREG->ScsiCNTL = 0L; \
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KeStallExecutionProcessor( 1000 )
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#define CARD_INITIALIZE(ChipAddr)
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#define CARD_DMA_INITIATE(ChipAddr, ToDevice)
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#define CARD_DMA_TERMINATE(ChipAddr)
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//
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// Define SCSI host adapter card configuration parameters.
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//
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#ifdef SCSI_VECTOR
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#undef SCSI_VECTOR
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#endif
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#ifdef SCSI_LEVEL
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#undef SCSI_LEVEL
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#endif
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#ifdef SCSI_PHYSICAL_BASE
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#undef SCSI_PHYSICAL_BASE
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#endif
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//
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// Define for LOCAL0 register
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//
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#define SCSI_LEVEL LOCAL0_LEVEL
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#define SCSI_VECTOR SGI_VECTOR_SCSI
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#define SCSI_BUS_INTERFACE Internal
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//
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// Define SCSI DMA channel.
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//
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#define CARD_DMA_REQUEST SGI_SCSI_DMA_CHANNEL
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#define CARD_DMA_WIDTH Width32Bits;
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#define CARD_DMA_SPEED TypeA;
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//
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// Define the default physical base address for SCSI controller.
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//
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#define SCSI_PHYSICAL_BASE SGI_SCSI0_WD_BASE
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#endif
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