828 lines
23 KiB
C
828 lines
23 KiB
C
/*+
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* file: d21x4def.h
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*
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* Copyright (C) 1992-1995 by
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* Digital Equipment Corporation, Maynard, Massachusetts.
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* All rights reserved.
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*
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* This software is furnished under a license and may be used and copied
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* only in accordance of the terms of such license and with the
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* inclusion of the above copyright notice. This software or any other
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* copies thereof may not be provided or otherwise made available to any
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* other person. No title to and ownership of the software is hereby
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* transferred.
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*
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* The information in this software is subject to change without notice
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* and should not be construed as a commitment by digital equipment
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* corporation.
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*
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* Digital assumes no responsibility for the use or reliability of its
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* software on equipment which is not supplied by digital.
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*
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*
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* Abstract: This file contains the definitions of the macros used by
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* the NDIS 4.0 miniport driver for DEC's DC21X4 PCI Ethernet
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* Adapter family
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*
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* Author: Philippe Klein
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*
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* Revision History:
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*
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* phk 28-Aug-1994 Initial entry
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*
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-*/
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// NDIS Revision level
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#define DC21X4_NDIS_MAJOR_VERSION 4
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#define DC21X4_NDIS_MINOR_VERSION 0
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// static is defined as EXTERN during the debug phase to allow
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// breakpoints to be set on them.
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#define DC21X4_DEVL 0
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//Filtering mode
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typedef enum _FILTERING_MODE {
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DC21X4_PERFECT_FILTERING,
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DC21X4_HASH_FILTERING
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} FILTERING_MODE;
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//CAM load
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typedef enum _LOAD_CAM {
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LOAD_COMPLETED,
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LOAD_PENDING,
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LOAD_IN_PROGRESS
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} LOAD_CAM;
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// Packet Type
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typedef enum _PACKET_TYPE {
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TXM_DIRECTED_FRAME,
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TXM_MULTICAST_FRAME,
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TXM_BROADCAST_FRAME,
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RCV_DIRECTED_FRAME,
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RCV_MULTICAST_FRAME,
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RCV_BROADCAST_FRAME,
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} PACKET_TYPE;
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//LINK STATUS
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typedef enum _LINK_STATUS {
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LinkFail=0,
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LinkPass,
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MiiLinkPass
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} LINK_STATUS;
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//TIMER
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typedef enum _TIMER_FLAG {
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NoTimer=0,
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SpaTimer,
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AncTimeout,
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DeferredLinkCheck,
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AncPolling,
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DeferredAnc
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} TIMER_FLAG;
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//INTERRUPT
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typedef enum _INTERRUPT_MSK {
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NoInterruptMasked=0,
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TxmInterruptMasked,
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TxmRcvInterruptMasked
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} INTERRUPT_MSK;
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typedef enum _LINK_HANDLER_MODE {
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NoNway,
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NwayWorkAround,
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Nway,
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FullNway
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} LINK_HANDLER_MODE;
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//SEND MODE
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typedef enum _SEND_MODE {
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CopyMinBuffer,
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CopyMaxBuffer,
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MappedBuffer
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} SEND_MODE;
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// Error log values
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#define DC21X4_ERRMSG_REGISTRY (ULONG)0x01
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#define DC21X4_ERRMSG_ALLOC_MEMORY (ULONG)0x02
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#define DC21X4_ERRMSG_SROM (ULONG)0x03
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#define DC21X4_ERRMSG_MEDIA (ULONG)0x04
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#define DC21X4_ERRMSG_LOAD_CAM (ULONG)0x05
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#define DC21X4_ERRMSG_INIT_DEVICE (ULONG)0x06
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#define DC21X4_ERRMSG_SYSTEM_ERROR (ULONG)0x07
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#define DC21X4_ERRMSG_TXM_JABBER_TIMEOUT (ULONG)0x08
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#define min(a,b) ((a)<(b) ? (a) : (b))
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#define max(a,b) ((a)>(b) ? (a) : (b))
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// OID parsing
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#define OID_TYPE_MASK 0xffff0000
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#define OID_TYPE_GENERAL_OPERATIONAL 0x00010000
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#define OID_TYPE_GENERAL_STATISTICS 0x00020000
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#define OID_TYPE_802_3_OPERATIONAL 0x01010000
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#define OID_TYPE_802_3_STATISTICS 0x01020000
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#define OID_REQUIRED_MASK 0x0000ff00
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#define OID_REQUIRED_MANDATORY 0x00000100
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#define OID_REQUIRED_OPTIONAL 0x00000200
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#define OID_INDEX_MASK 0x000000ff
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// Indexes in the GeneralMandatory array.
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#define GM_TRANSMIT_OK 0x00
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#define GM_RECEIVE_OK 0x01
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#define GM_TRANSMIT_ERROR 0x02
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#define GM_RECEIVE_ERROR 0x03
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#define GM_MISSED_FRAMES 0x04
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#define GM_ARRAY_SIZE 0x05
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// Indexes in the GeneralOptional array.
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#define GO_DIRECTED_TRANSMITS 0x00
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#define GO_MULTICAST_TRANSMITS 0x01
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#define GO_BROADCAST_TRANSMITS 0x02
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#define GO_DIRECTED_RECEIVES 0x00
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#define GO_MULTICAST_RECEIVES 0x01
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#define GO_BROADCAST_RECEIVES 0x02
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#define GO_COUNT_ARRAY_SIZE 0x06
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#define GO_RECEIVE_CRC_ERROR 0x00
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#define GO_TRANSMIT_QUEUE_LENGTH 0x01
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#define GO_ARRAY_SIZE 0x02
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// Indexes in the MediaMandatory array.
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#define MM_RECEIVE_ALIGNMENT_ERROR 0x00
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#define MM_TRANSMIT_ONE_COLLISION 0x01
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#define MM_TRANSMIT_MULT_COLLISIONS 0x02
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#define MM_ARRAY_SIZE 0x03
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// Indexes in the MediaOptional array
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#define MO_TRANSMIT_DEFERRED 0x00
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#define MO_TRANSMIT_EXC_COLLISIONS 0x01
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#define MO_RECEIVE_OVERFLOW 0x02
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#define MO_TRANSMIT_UNDERRUN 0x03
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#define MO_TRANSMIT_HEARTBEAT_FAILURE 0x04
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#define MO_TRANSMIT_CRS_LOST 0x05
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#define MO_TRANSMIT_LATE_COLLISION 0x06
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#define MO_ARRAY_SIZE 0x07
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// 64_bit counter
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typedef struct _DC21X4_LARGE_INTEGER {
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ULONG LowPart;
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ULONG HighPart;
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} DC21X4_LARGE_INTEGER, *PDC21X4_LARGE_INTEGER;
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// GeneralOptional counters
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typedef struct _GEN_OPTIONAL_COUNT{
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DC21X4_LARGE_INTEGER ByteCount;
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ULONG FrameCount;
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} GEN_OPTIONAL_COUNT, *PGEN_OPTIONAL_COUNT;
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// This type defines the physical addresses used by DC21X4
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typedef ULONG DC21X4_PHYSICAL_ADDRESS,*PDC21X4_PHYSICAL_ADDRESS;
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// Receive descriptor
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typedef struct _DC21X4_RECEIVE_DESCRIPTOR {
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ULONG Status; // Status bits returned upon completion
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ULONG Control; // Control bits and byte_counts
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DC21X4_PHYSICAL_ADDRESS FirstBufferAddress; // First Buffer Address
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DC21X4_PHYSICAL_ADDRESS SecondBufferAddress; // Second Buffer Address
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// Driver's reserved field (12 ULONG max)
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struct _DC21X4_RECEIVE_DESCRIPTOR *Next; // Next Descriptor;
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struct _RCV_HEADER *RcvHeader;
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} DC21X4_RECEIVE_DESCRIPTOR, *PDC21X4_RECEIVE_DESCRIPTOR;
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// Transmit descriptor
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typedef struct _DC21X4_TRANSMIT_DESCRIPTOR {
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ULONG Status; // Status bits returned upon completion
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ULONG Control; // Control bits and byte_counts
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DC21X4_PHYSICAL_ADDRESS FirstBufferAddress; // First Buffer Address
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DC21X4_PHYSICAL_ADDRESS SecondBufferAddress; // Second Buffer Address
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// Driver's reserved field (12 ULONG max)
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ULONG DescriptorPa; // Descriptor's Physical Address
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ULONG MapTableIndex; // index into the Mapping Table
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struct _DC21X4_TRANSMIT_DESCRIPTOR *Next; // Next Descriptor;
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struct _DC21X4_TRANSMIT_DESCRIPTOR *DescPointer; // Pointer to the first or last segment's desc.
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PNDIS_PACKET Packet; // Pointer to the packet mapped by this descriptor
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USHORT PacketSize; // Size of the packet
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UCHAR PacketType; // Packet Type (Directed,Multicast,...)
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UCHAR SendStatus; // Status
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} DC21X4_TRANSMIT_DESCRIPTOR, *PDC21X4_TRANSMIT_DESCRIPTOR;
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#define DC21X4_MAX_MULTICAST_ADDRESSES 36 // This number is arbitrary
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// and can be increased if needed
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// Number of entries in the Setup buffer.
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#define DC21X4_SETUP_PERFECT_ENTRIES 16
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#define DC21X4_SETUP_HASH_ENTRIES 512
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// Maximum number of multicast address for Perfect filtering
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// The two first addresses are reserved for the adapter and the
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// Broadcast addresses
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#define DC21X4_MAX_MULTICAST_PERFECT 14
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// Setup buffer
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//
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// In perfect filtering mode, the setup buffer
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// contains 16 Ethernet address
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// The Ethernet address, divided into three pieces in
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// order from most significant to least significant.
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// In each piece only the low-order 16 bits are used.
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// For example address A8-09-65-12-34-36 will be stored as
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// 0x000009A8
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// 0x00001265
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// 0x00007634
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//
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// In Hashing mode , the setup buffer contains
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// a single physical address and a 512_bit hash filter
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typedef union _DC21X4_SETUP_BUFFER {
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struct {
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ULONG PhysicalAddress[DC21X4_SETUP_PERFECT_ENTRIES][3];
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} Perfect;
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struct {
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ULONG Filter[32];
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ULONG Mbz1[7];
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ULONG PhysicalAddress[3];
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ULONG Mbz2[6];
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} Hash;
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} DC21X4_SETUP_BUFFER, *PDC21X4_SETUP_BUFFER;
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// **********************************************************************
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// DC21X4 PCI configuration space
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// **********************************************************************
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#define CFID 0 //ID Register
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#define CFCS 1 //Command/Status Register
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#define CFRV 2 //Revision Register
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#define CFLT 3 //Latency Timer Register
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#define CBIO 4 //Base I/O Address Register
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#define CBMA 5 //Base Memory Address Register
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#define SSID 11 //Subsystem ID Register
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#define CBER 12 //Expansion ROM Address Register
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#define CFIT 15 //Interrupt Register
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#define CFDA 16 //Driver Area register
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#define PCI_CONFIG_SIZE 17
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typedef struct _DC21X4_PCI_CONFIGURATION {
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ULONG Reg[PCI_CONFIG_SIZE];
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}DC21X4_PCI_CONFIGURATION, *PDC21X4_PCI_CONFIGURATION;
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// **********************************************************************
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// DC21X4 configuration
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// Hold the values of the Registry keys
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// **********************************************************************
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typedef struct _DC21X4_CONFIGURATION {
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BOOLEAN Present; // Registry key status
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ULONG RegistryValue; // Registry Value
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ULONG CsrValue; // Csr Value
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}DC21X4_CONFIGURATION, *PDC21X4_CONFIGURATION;
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// **********************************************************************
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// Allocation Map
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//
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// This structure holds the mapping parameters of a structure allocated
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// in memory
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// **********************************************************************
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typedef struct _ALLOCATION_MAP {
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ULONG AllocVa; // virtual address of the memory block allocated to the structure
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NDIS_PHYSICAL_ADDRESS AllocPa; // physical address of the memory block allocated to the structure
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ULONG AllocSize; // size of the allocated block
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ULONG Va; // virtual address of the aligned structure
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ULONG Pa; // physical address of the aligned structure
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ULONG Size; // size of the structure
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PNDIS_BUFFER FlushBuffer; // NDIS Flush Buffer
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} ALLOCATION_MAP,*PALLOCATION_MAP;
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// **********************************************************************
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// Header for receive buffers so that we can keep track of them
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// **********************************************************************
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typedef struct _RCV_HEADER {
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ALLOCATION_MAP;
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struct _RCV_HEADER *Next; // Pointer to the next receive buffer.
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PNDIS_PACKET Packet; // NDIS packet associated with the buffer.
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#if DBG
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ULONG Signature; // Used to identify the receive header.
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#endif
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}RCV_HEADER,*PRCV_HEADER;
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#define RCV_HEADER_SIZE (sizeof(RCV_HEADER))
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// Reserved section for receive packets
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// that are released up to the bindings.
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typedef struct _RCV_PACKET_RESERVED {
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PRCV_HEADER RcvHeader;
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union {
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PNDIS_PACKET Next;
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PDC21X4_RECEIVE_DESCRIPTOR Descriptor;
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};
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} RCV_PACKET_RESERVED,*PRCV_PACKET_RESERVED;
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#define RCV_RESERVED(x) ((PRCV_PACKET_RESERVED)(x)->MiniportReserved)
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#define MAX_PACKET_ARRAY 32
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// **********************************************************************
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// DC21X4 Physical Mapping
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//
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// Holds the physical mapping information
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// **********************************************************************
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typedef struct _PHYSICAL_MAPPING {
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ULONG Register;
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PNDIS_BUFFER Buffer;
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BOOLEAN Valid;
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}PHYSICAL_MAPPING, *PPHYSICAL_MAPPING;
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// **********************************************************************
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// DC21X4 Media Table
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//
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// Holds the media programming values
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// **********************************************************************
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typedef struct _MEDIA_TABLE {
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ULONG GeneralPurposeCtrl;
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ULONG GeneralPurposeData;
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ULONG SiaRegister[3];
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ULONG Mode;
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ULONG Polarity;
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ULONG SenseMask;
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}MEDIA_TABLE, *PMEDIA_TABLE;
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// **********************************************************************
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// DC21X4 PHY Table
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//
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// Holds the PHY values
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// **********************************************************************
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typedef struct _PHY_TABLE {
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BOOLEAN Present;
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INT GepSequenceLength;
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INT ResetSequenceLength;
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USHORT MediaCapabilities;
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USHORT NwayAdvertisement;
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USHORT FullDuplexBits;
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USHORT TxThresholdModeBits;
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||
USHORT GeneralPurposeCtrl;
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USHORT GepSequence[MAX_GPR_SEQUENCE];
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UCHAR ResetSequence[MAX_RESET_SEQUENCE];
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ULONG GepInterruptMask;
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||
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}PHY_TABLE, *PPHY_TABLE;
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// *******************************************************************
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// DC21X4_ADAPTER
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//
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// This Adapter block contains the state of an adapter.
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// Initialized during the adapter registration.
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//
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// *******************************************************************
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typedef struct _DC21X4_ADAPTER {
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NDIS_HANDLE MiniportAdapterHandle; // Handle given by NDIS when the adapter is registered.
|
||
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NDIS_HANDLE FlushBufferPoolHandle; // Handle returned by NDIS which
|
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// identifies a pool of flush buffers
|
||
|
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NDIS_MINIPORT_INTERRUPT Interrupt; // Holds the interrupt object for this adapter.
|
||
|
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NDIS_MINIPORT_TIMER Timer; // Holds the timer object
|
||
NDIS_MINIPORT_TIMER MonitorTimer;
|
||
NDIS_MINIPORT_TIMER ResetTimer;
|
||
|
||
UINT LinkCheckCount;
|
||
|
||
NDIS_SPIN_LOCK EnqueueSpinLock; // Send/Request SpinLock
|
||
NDIS_SPIN_LOCK FullDuplexSpinLock; // Send/Receive SpinLock
|
||
|
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ULONG AdapterType; // The type of the adapter (EISA,PCI,...)
|
||
ULONG DeviceId; // The adapter CFID
|
||
ULONG SlotNumber; // The Slot Number of this adapter;
|
||
UINT RevisionNumber; // The Revision Number of this adapter
|
||
|
||
BOOLEAN InterruptLatched;
|
||
BOOLEAN PermanentAddressValid;
|
||
BOOLEAN FullDuplex;
|
||
BOOLEAN FullDuplexLink;
|
||
BOOLEAN DynamicAutoSense;
|
||
BOOLEAN DefaultMediumFlag;
|
||
BOOLEAN ParityError;
|
||
BOOLEAN ResetInProgress;
|
||
BOOLEAN Initializing;
|
||
BOOLEAN MediaNway;
|
||
BOOLEAN NwayEnabled;
|
||
BOOLEAN NwayProtocol;
|
||
BOOLEAN FirstAncInterrupt;
|
||
INT AutoNegotiationCount;
|
||
BOOLEAN OverflowWorkAround;
|
||
BOOLEAN IndicateOverflow;
|
||
|
||
UINT LinkStatus;
|
||
UINT PreviousLinkStatus;
|
||
|
||
ULONG LinkSpeed;
|
||
|
||
INT TransceiverDelay;
|
||
|
||
ULONG PciRegMap[DC21X4_MAX_CONFIGURATION]; // Pci Configuration Register Mapping
|
||
ULONG CsrMap[DC21X4_MAX_CSR]; // DC21X4 Csr Mapping
|
||
|
||
// The burnt-in network address from the hardware.
|
||
UCHAR PermanentNetworkAddress[ETH_LENGTH_OF_ADDRESS];
|
||
|
||
// The current network address from the hardware.
|
||
UCHAR CurrentNetworkAddress[ETH_LENGTH_OF_ADDRESS];
|
||
|
||
ULONG MaxMulticastAddresses;
|
||
|
||
|
||
ULONG CacheLineSize; // The size of the Cache lines
|
||
|
||
ULONG PciCommand;
|
||
ULONG PciLatencyTimer;
|
||
ULONG PciDriverArea;
|
||
|
||
ULONG IOBaseAddress; // Base address of the DC21X4 ports.
|
||
ULONG PortOffset;
|
||
ULONG IOSpace;
|
||
|
||
ULONG OperationMode;
|
||
ULONG InterruptMask;
|
||
ULONG BusMode;
|
||
|
||
ULONG Gep_Sia2;
|
||
|
||
UINT MediaType; // DC21X4 Connection mode
|
||
UINT MediaCapable;
|
||
INT DefaultMedium;
|
||
INT SelectedMedium;
|
||
INT MediaCount;
|
||
|
||
INT MediaPrecedence[MAX_MEDIA_TABLE]; // Hold the Media precedences
|
||
MEDIA_TABLE Media[MAX_MEDIA_TABLE]; // Hold the Media parameters
|
||
|
||
BOOLEAN PhyMediumInSrom; // Phy medium listed in SROM
|
||
BOOLEAN PhyPresent; // Phy adapter present
|
||
BOOLEAN PhyNwayCapable;
|
||
BOOLEAN Indicate10BTLink;
|
||
BOOLEAN Force10;
|
||
|
||
UINT PhyNumber;
|
||
UINT MiiMediaType; // DC21X4 MiiConnection mode
|
||
|
||
MII_GEN_INFO MiiGen; // Hold the PHY information
|
||
PHY_TABLE Phy[MAX_PHY_TABLE]; // Hold the PHY parameters
|
||
|
||
BOOLEAN IgnoreTimer;
|
||
INT TimerFlag;
|
||
INT PollCount;
|
||
|
||
NDIS_PHYSICAL_ADDRESS HighestAllocAddress; // Upper boundary for allocation
|
||
|
||
ULONG InterruptStatus; // Holds a value of the interrupt status
|
||
// (set by the ISR, cleared by the
|
||
// interrupt handler routine)
|
||
|
||
ULONG SiaStatus; // Holds the value of the SIA status
|
||
|
||
|
||
UINT DescriptorSize; // The size of a descriptor entry into the descriptor ring
|
||
// (Reflects bus_mode<skip_length>)
|
||
|
||
UINT FilteringMode; // Filtering mode (Perfect/Hashing)
|
||
UINT FilterClass; // Filter class
|
||
|
||
ALLOCATION_MAP DescriptorRing; // Descriptor Ring Allocation Map
|
||
|
||
ULONG ReceiveDescriptorRingVa; // Receive Descriptor Ring Virtual Address
|
||
ULONG ReceiveDescriptorRingPa; // Receive Descriptor Ring Physical Address
|
||
ALLOCATION_MAP RcvBufferSpace;
|
||
|
||
PDC21X4_RECEIVE_DESCRIPTOR DequeueReceiveDescriptor;
|
||
|
||
UINT ReceiveRingSize; // Receive Descriptor Ring Size
|
||
|
||
ULONG TransmitDescriptorRingVa; // Transmit Descriptor Ring Virtual Address
|
||
ULONG TransmitDescriptorRingPa; // Transmit Descriptor Ring Physical Address
|
||
|
||
BOOLEAN DisableTransmitPolling; // Transmit Polling Flag
|
||
|
||
ALLOCATION_MAP
|
||
MaxTransmitBuffer[DC21X4_NUMBER_OF_MAX_TRANSMIT_BUFFERS];
|
||
|
||
ALLOCATION_MAP
|
||
MinTransmitBuffer[DC21X4_NUMBER_OF_MIN_TRANSMIT_BUFFERS];
|
||
BOOLEAN DontUseMinTransmitBuffer;
|
||
|
||
ULONG SetupBufferVa; // Setup Buffer Virtual address
|
||
ULONG SetupBufferPa; // Setup Buffer Physical address
|
||
|
||
PHYSICAL_MAPPING
|
||
PhysicalMapping [TRANSMIT_RING_SIZE * NUMBER_OF_SEGMENT_PER_DESC];
|
||
|
||
PDC21X4_TRANSMIT_DESCRIPTOR EnqueueTransmitDescriptor;
|
||
PDC21X4_TRANSMIT_DESCRIPTOR DequeueTransmitDescriptor;
|
||
UINT FreeTransmitDescriptorCount; // Free Transmit Descriptor Count
|
||
|
||
UINT AllocMapRegisters; // Allocated Map Registers
|
||
UINT FreeMapRegisters; // Free Map Register count
|
||
UINT MapRegisterIndex;
|
||
|
||
UINT TxmThreshold; // Transmit threshold
|
||
ULONG Threshold10Mbps; // Threshold 10Mbps
|
||
ULONG Threshold100Mbps; // Threshold 100Mbps
|
||
ULONG TransmitDefaultDescriptorErrorMask; // Transmit Descriptor Error bit mask
|
||
ULONG TransmitDescriptorErrorMask; // Transmit Descriptor Error bit mask
|
||
|
||
UINT PhysicalSegmentThreshold;
|
||
|
||
UINT MaxTransmitBufferIndex; // Max Transmit Buffer Index;
|
||
UINT MaxTransmitBufferInUse; // Max Transmit Buffer Count;
|
||
|
||
UINT MinTransmitBufferIndex; // Min Transmit Buffer Index;
|
||
UINT MinTransmitBufferInUse; // Min Transmit Buffer Count;
|
||
|
||
UINT NoCarrierCount;
|
||
UINT ExcessCollisionsCount;
|
||
UINT UnderrunRetryCount;
|
||
UINT UnderrunMaxRetries;
|
||
UINT UnderrunThreshold;
|
||
|
||
|
||
ULONG InterruptModeration;
|
||
ULONG Polling;
|
||
ULONG TxmPolling;
|
||
ULONG RcvTxmPolling;
|
||
|
||
INT InterruptThreshold;
|
||
INT InterruptCount;
|
||
INT LastInterruptCount;
|
||
|
||
INT FrameThreshold;
|
||
INT FrameCount;
|
||
|
||
ULONG TiPeriod; // Transmit Interrupt period
|
||
ULONG TiCount; // Transmit interrupt period counter
|
||
|
||
ULONG SoftwareCRC; // CRC Sofware generation mode
|
||
|
||
INT TransmitFrameCount; // Holds the last snapshoted Txm frame count
|
||
INT ReceiveFrameCount; // Holds the last snapshoted Rcv frame count
|
||
|
||
ULONG LinkHandlerMode;
|
||
|
||
|
||
UINT RcvHeaderSize;
|
||
|
||
// Information for releasing of the receive buffers.
|
||
|
||
NDIS_HANDLE ReceivePacketPool;
|
||
ULONG ExtraReceivePackets;
|
||
PNDIS_PACKET FreePacketList;
|
||
PNDIS_PACKET PacketArray[MAX_PACKET_ARRAY];
|
||
|
||
ULONG ExtraReceiveBuffers;
|
||
PRCV_HEADER FreeRcvList;
|
||
ULONG CurrentReceiveBufferCount;
|
||
ULONG NeededReceiveBuffers;
|
||
|
||
|
||
// Adapter statistics
|
||
|
||
ULONG GeneralMandatory[GM_ARRAY_SIZE];
|
||
|
||
GEN_OPTIONAL_COUNT GeneralOptionalCount[GO_COUNT_ARRAY_SIZE];
|
||
|
||
ULONG GeneralOptional[GO_ARRAY_SIZE];
|
||
|
||
ULONG MediaMandatory[MM_ARRAY_SIZE];
|
||
ULONG MediaOptional[MO_ARRAY_SIZE];
|
||
|
||
|
||
} DC21X4_ADAPTER,*PDC21X4_ADAPTER;
|
||
|
||
// **********************************************************************
|
||
// DC21X4_SYNCH_CONTEXT
|
||
//
|
||
//Context structure while synchronizing with interrupt
|
||
//
|
||
// **********************************************************************
|
||
|
||
typedef struct _DC21X4_SYNCH_CONTEXT {
|
||
|
||
PDC21X4_ADAPTER Adapter;
|
||
ULONG IsrStatus;
|
||
|
||
} DC21X4_SYNCH_CONTEXT,*PDC21X4_SYNCH_CONTEXT;
|
||
|
||
// **********************************************************************
|
||
// CHECKSUM structure
|
||
//
|
||
// Structure for holding checksum and its status when reading the SROM.
|
||
//
|
||
// **********************************************************************
|
||
|
||
typedef struct _CHECKSUM
|
||
{
|
||
USHORT Accumulator;
|
||
USHORT Value;
|
||
UCHAR Status;
|
||
} CHECKSUM, *PCHECKSUM;
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
// Macros used for memory allocation and deallocation.
|
||
|
||
#define ALLOC_MEMORY(Status, Address, Length) { \
|
||
\
|
||
NDIS_PHYSICAL_ADDRESS HighestAddress; \
|
||
NdisSetPhysicalAddressLow(HighestAddress,0xffffffff); \
|
||
NdisSetPhysicalAddressHigh(HighestAddress,0xffffffff); \
|
||
*(Status) = NdisAllocateMemory((PVOID)(Address), \
|
||
(UINT)(Length), \
|
||
0, \
|
||
HighestAddress \
|
||
); \
|
||
}
|
||
|
||
#define FREE_MEMORY(Address, Length) \
|
||
\
|
||
NdisFreeMemory((PVOID)(Address), \
|
||
(UINT)(Length), \
|
||
0 \
|
||
)
|
||
|
||
#define MOVE_MEMORY(Destination,Source,Length) \
|
||
\
|
||
NdisMoveMemory((PVOID)(Destination), \
|
||
(PVOID)(Source), \
|
||
(ULONG)(Length) \
|
||
) \
|
||
|
||
#define ZERO_MEMORY(Destination,Length) \
|
||
\
|
||
NdisZeroMemory((PVOID)(Destination), \
|
||
(ULONG)(Length) \
|
||
)
|
||
|
||
|
||
// 64_bit counter addition
|
||
|
||
#define ADD_ULONG_TO_LARGE_INTEGER(LargeInteger,Ulong ) { \
|
||
(LargeInteger).LowPart += (Ulong); \
|
||
if ((LargeInteger).LowPart < (Ulong)) \
|
||
(LargeInteger).HighPart++; \
|
||
}
|
||
|
||
//Frame type
|
||
|
||
#define IS_MULTICAST(_addr) \
|
||
((*(UNALIGNED UCHAR *)(_addr) & 1) == 1)
|
||
|
||
#define IS_BROADCAST(_addr) \
|
||
( (*(UNALIGNED ULONG *)(_addr) == 0xffffffff) && \
|
||
(*(UNALIGNED USHORT *)((UINT)(_addr) + 4) == 0xffff) \
|
||
)
|
||
|
||
#define CHECK_PACKET_TYPE(dst) \
|
||
( IS_MULTICAST(dst) ? \
|
||
( IS_BROADCAST(dst) ? TXM_BROADCAST_FRAME : \
|
||
TXM_MULTICAST_FRAME) : TXM_DIRECTED_FRAME \
|
||
)
|
||
|
||
#define IS_NULL_ADDRESS(_addr) \
|
||
( (*(UNALIGNED ULONG *)(_addr) == 0) && \
|
||
(*(UNALIGNED USHORT *)((UINT)(_addr) + 4) == 0) \
|
||
)
|