425 lines
11 KiB
C
425 lines
11 KiB
C
/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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wdlmireg.h
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Abstract:
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Register definitions and values for the many cards
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Author:
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Sean Selitrennikoff (seanse) 15-Jan-92
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Environment:
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Kernel mode, FSD
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Revision History:
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--*/
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//
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// Microchannel Bus registers
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//
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#define CHANNEL_SELECT_REG 0x96
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#define LSB_ID_POS_REG 0x100
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#define MSB_ID_POS_REG 0x101
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#define IO_BASE_POS_REG 0x102
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#define RAM_BASE_POS_REG 0x103
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#define BIOS_ROM_POS_REG 0x104
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#define IRQ_POS_REG 0x105
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//
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// Microchannel 83c593 Registers.
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//
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#define MEMORY_ENABLE_RESET_REG 0x00
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#define EEPROM_CONTROL_REG 0x01
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#define BOARD_ID_REG0 0x02
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#define BOARD_ID_REG1 0x03
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#define INTERRUPT_CONTROL_AND_STATUS_REG 0x04
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#define COMMUNICATION_CONTROL_REG 0x05
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#define FIFO_ENTRY_EXIT_REG 0x06
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#define GENERAL_PURPOSE_REG 0x07
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//
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// Microchannel 83c594 Registers
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#define REVISION_REG 0x07
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//
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// AT Bus Registers
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//
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//
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// 83c583 registers
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//
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#define BASE_REG 0x00
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#define MEMORY_SELECT_REG 0x00 // MSR
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#define INTERFACE_CONFIG_REG 0x01 // ICR
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#define BUS_SIZE_REG 0x01 // BSR (read only)
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#define IO_ADDRESS_REG 0x02 // IAR
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#define BIOS_ROM_ADDRESS_REG 0x03 // BIO (583, 584)
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#define EEPROM_ADDRESS_REG 0x03 // EAR (584)
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#define INTERRUPT_REQUEST_REG 0x04 // IRR
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#define GENERAL_PURPOSE_REG1 0x05 // GP1
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#define LA_ADDRESS_REG 0x05 // LAAR (write only)
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#define IO_DATA_LATCH_REG 0x06 // IOD (583)
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#define INITIALIZE_JUMPER_REG 0x06 // IJR (584)
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#define GENERAL_PURPOSE_REG2 0x07 // GP2
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#define LAN_ADDRESS_REG 0x08 // LAR
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#define LAN_ADDRESS_REG2 0x09 // LAR2
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#define LAN_ADDRESS_REG3 0x0A // LAR3
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#define LAN_ADDRESS_REG4 0x0B // LAR4
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#define LAN_ADDRESS_REG5 0x0C // LAR5
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#define LAN_ADDRESS_REG6 0x0D // LAR6
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#define LAN_ADDRESS_REG7 0x0E // LAR7
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#define LAN_ADDRESS_REG8 0x0F // LAR8
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//
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// 8390 Registers
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//
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#define OFF_8390_REG 0x10 // offset of the 8390 chip
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// page 0, reading
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#define COMMAND_REG OFF_8390_REG + 0x00
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#define DMA_ADDRESS_0_REG OFF_8390_REG + 0x01
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#define DMA_ADDRESS_1_REG OFF_8390_REG + 0x02
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#define BOUNDARY_REG OFF_8390_REG + 0x03
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#define TRANSMIT_STATUS_REG OFF_8390_REG + 0x04
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#define NUM_COLLISIONS_REG OFF_8390_REG + 0x05
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#define FIFO_REG OFF_8390_REG + 0x06
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#define INTERRUPT_STATUS_REG OFF_8390_REG + 0x07
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#define REMOTE_DMA_ADDRESS_0_REG OFF_8390_REG + 0x08
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#define REMOTE_DMA_ADDRESS_1_REG OFF_8390_REG + 0x09
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#define RECEIVE_STATUS_REG OFF_8390_REG + 0x0C
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#define ALIGNMENT_ERROR_REG OFF_8390_REG + 0x0D
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#define CRC_ERROR_REG OFF_8390_REG + 0x0E
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#define MISSED_PACKET_REG OFF_8390_REG + 0x0F
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// page 0, writing
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#define COMMAND_REG OFF_8390_REG + 0x00
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#define PAGE_START_REG OFF_8390_REG + 0x01
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#define PAGE_STOP_REG OFF_8390_REG + 0x02
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#define TRANSMIT_PAGE_START_REG OFF_8390_REG + 0x04
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#define TRANSMIT_BYTE_COUNT_REG0 OFF_8390_REG + 0x05
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#define TRANSMIT_BYTE_COUNT_REG1 OFF_8390_REG + 0x06
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#define REMOTE_START_ADDRESS_REG0 OFF_8390_REG + 0x08
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#define REMOTE_START_ADDRESS_REG1 OFF_8390_REG + 0x09
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#define REMOTE_BYTE_COUNT_REG0 OFF_8390_REG + 0x0A
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#define REMOTE_BYTE_COUNT_REG1 OFF_8390_REG + 0x0B
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#define RECEIVE_CONFIG_REG OFF_8390_REG + 0x0C
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#define TRANSMIT_CONFIG_REG OFF_8390_REG + 0x0D
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#define DATA_CONFIG_REG OFF_8390_REG + 0x0E
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#define INTERRUPT_MASK_REG OFF_8390_REG + 0x0F
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// page 1, reading and writing
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#define CONTROL_REG OFF_8390_REG + 0x00
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#define PHYSICAL_ADDRESS_REG0 OFF_8390_REG + 0x01
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#define PHYSICAL_ADDRESS_REG1 OFF_8390_REG + 0x02
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#define PHYSICAL_ADDRESS_REG2 OFF_8390_REG + 0x03
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#define PHYSICAL_ADDRESS_REG3 OFF_8390_REG + 0x04
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#define PHYSICAL_ADDRESS_REG4 OFF_8390_REG + 0x05
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#define PHYSICAL_ADDRESS_REG5 OFF_8390_REG + 0x06
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#define CURRENT_BUFFER_REG OFF_8390_REG + 0x07
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#define MULTICAST_ADDRESS_REG0 OFF_8390_REG + 0x08
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#define MULTICAST_ADDRESS_REG1 OFF_8390_REG + 0x09
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#define MULTICAST_ADDRESS_REG2 OFF_8390_REG + 0x0A
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#define MULTICAST_ADDRESS_REG3 OFF_8390_REG + 0x0B
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#define MULTICAST_ADDRESS_REG4 OFF_8390_REG + 0x0C
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#define MULTICAST_ADDRESS_REG5 OFF_8390_REG + 0x0D
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#define MULTICAST_ADDRESS_REG6 OFF_8390_REG + 0x0E
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#define MULTICAST_ADDRESS_REG7 OFF_8390_REG + 0x0F
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// page 2, reading and writing
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#define BLOCK_ADDRESS_REG OFF_8390_REG + 0x06
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#define ENHANCEMENT_REG OFF_8390_REG + 0x07
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//
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// Register Bit Definitions
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//
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//
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// Microchannel Registers
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//
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#define NUMBER_OF_CHANNELS 8
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#define DISABLE_BIOS 0x02
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#define DISABLE_SETUP 0x00
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#define SELECT_CHANNEL_1 0x08
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#define ADAPTER_ID_MSB 0x6F
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#define ADAPTER_ID_LSB0 0xC0
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#define ADAPTER_ID_LSB1 0xC1
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#define ADAPTER_ID_LSB2 0xC2
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#define ADAPTER_ID_LSB3 0xC3
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#define ADAPTER_ID_LSB4 0xC4
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#define ADAPTER_ID_LSB5 0xC5
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#define ADAPTER_ID_LSB6 0xC6
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//
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// BISTRO ID BYTES
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//
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#define BISTRO_ID_MSB 0xEF
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#define BISTRO_ID_LSB 0xE5
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#define ALT_BISTRO_ID_LSB 0xD5
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//
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// COMMUNICATION_CONTROL_REG
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//
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#define CCR_INTERRUPT_ENABLE 0x04
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//
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// AT bus Registers
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//
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//
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// MSR
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//
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#define RESET 0x80 // 1 == reset
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#define MEMORY_ENABLE 0x40 // 1 == enabled
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#define ADDRESS_BIT18 0x20 // Top bits for shared memory address
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#define ADDRESS_BIT17 0x10 // Assume bit 19 == 1
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#define ADDRESS_BIT16 0x08
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#define ADDRESS_BIT15 0x04
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#define ADDRESS_BIT14 0x02
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#define ADDRESS_BIT13 0x01
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//
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// ICR
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//
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#define STORE 0x80 // Store into EEProm
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#define RECALL 0x40 // Recall from EEProm
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#define RECALL_ALL_BUT_IO 0x20 // Recall all but IO and LAN Address
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#define RECALL_LAN 0x10 // Recall LAN Address
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#define MEMORY_SIZE 0x08 // Shared Memory size
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#define DMA_ENABLE 0x04 // DMA Enable (583)
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#define IR2 0x04 // IRQ index MSB (584)
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#define IO_PORT_ENABLE 0x02 // (583)
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#define OTHER 0x02 // (584)
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#define WORD_TRANSFER_SELECT 0x01
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//
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// BIO
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//
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#define BIOS_SIZE_BIT1 0x80
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#define BIOS_SIZE_BIT0 0x40
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#define BIOS_ROM_ADDRESS_BIT18 0x20
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#define BIOS_ROM_ADDRESS_BIT17 0x10
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#define BIOS_ROM_ADDRESS_BIT16 0x08
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#define BIOS_ROM_ADDRESS_BIT15 0x04
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#define BIOS_ROM_ADDRESS_BIT14 0x02
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#define W8003_INTERRUPT 0x01
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//
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// IRR
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//
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#define INTERRUPT_ENABLE 0x80
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#define INTERRUPT_REQUEST_BIT1 0x40
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#define INTERRUPT_REQUEST_BIT0 0x20
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#define ALTERNATE_MODE 0x10
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#define ALTERNATE_INTERRUPT 0x08
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#define BIOS_WAIT_STATE_BIT1 0x04
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#define BIOS_WAIT_STATE_BIT0 0x02
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#define ZERO_WAIT_STATE_ENABLE 0x01
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//
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// BSR
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//
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#define BUS_16_BIT 0x01
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//
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// LAAR
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//
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#define MEMORY_16BIT_ENABLE 0x80
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#define LAN_16BIT_ENABLE 0x40
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#define LAAR_ZERO_WAIT_STATE 0x20
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#define LAN_ADDRESS_BIT23 0x10
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#define LAN_ADDRESS_BIT22 0x08
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#define LAN_ADDRESS_BIT21 0x04
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#define LAN_ADDRESS_BIT20 0x02
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#define LAN_ADDRESS_BIT19 0x01
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#define LAAR_MASK 0x1F
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#define INIT_LAAR_VALUE 0x01 // To set bit 19 to 1
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//
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// 8390 Register Bit definitions
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//
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//
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// COMMAND_REG
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//
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#define STOP 0x01 // software reset
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#define START 0x02
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#define TRANSMIT_PACKET 0x04
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#define READ_0 0x08
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#define READ_1 0x10
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#define READ_2 0x20
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#define REMOTE_READ 0x08 // Remote DMA Command
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#define REMOTE_WRITE 0x10 // Remote DMA Command
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#define REMOTE_SEND_PACKET 0x18 // Remote DMA Command
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#define REMOTE_ABORT_COMPLETE 0x20 // Remote DMA Command
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#define PAGE_SELECT_0 0x00
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#define PAGE_SELECT_1 0x40
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#define PAGE_SELECT_2 0x80
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#define PAGE_SELECT_0_START 0x22
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#define PAGE_SELECT_1_START 0x62
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#define PAGE_SELECT_2_START 0xA2
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//
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// INTERRUPT_STATUS_REG
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//
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#define PACKET_RECEIVED_NO_ERROR 0x01
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#define PACKET_TRANSMITTED_NO_ERROR 0x02
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#define RECEIVE_ERROR 0x04
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#define TRANSMIT_ERROR 0x08
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#define OVERWRITE_WARNING 0x10
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#define ISR_COUNTER_OVERFLOW 0x20
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#define REMOTE_DMA_COMPLETE 0x40
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#define RESET_DONE 0x80
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//
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// INTERRUPT_MASK_REG
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//
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#define PACKET_RECEIVE_ENABLE 0x01
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#define PACKET_TRANSMIT_ENABLE 0x02
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#define RECEIVE_ERROR_ENABLE 0x04
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#define TRANSMIT_ERROR_ENABLE 0x08
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#define OVERWRITE_WARNING_ENABLE 0x10
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#define COUNTER_OVERFLOW_ENABLE 0x20
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#define REMOTE_DMA_COMPLETE_ENABLE 0x40
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//
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// DATA_CONFIG_REG
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//
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#define WORD_TRANSFER_SELECT 0x01
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#define BYTE_ORDER_SELECT 0x02
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#define LONG_ADDRESS_SELECT 0x04
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#define BURST_DMA_SELECT 0x08
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#define AUTO_INITIALIZE_REMOTE 0x10
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#define RECEIVE_FIFO_THRESHOLD_2 0x00
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#define RECEIVE_FIFO_THRESHOLD_4 0x20
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#define RECEIVE_FIFO_THRESHOLD_8 0x40
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#define RECEIVE_FIFO_THRESHOLD_12 0x80
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//
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// TRANSMIT_CONFIG_REG
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//
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#define MANUAL_CRC_GENERATION 0x01
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#define LOOPBACK_MODE1 0x02 // mode 1, no loopback
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#define LOOPBACK_MODE2 0x04 // mode 2, loopback
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#define LOOPBACK_MODE3 0x06 // mode 3, no loopback
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#define AUTO_TRANSMIT_DISABLE 0x08
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#define COLLISION_OFFSET_ENABLE 0x10
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//
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// TRANSMIT_STATUS_REG
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//
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#define TRANSMIT_NO_ERROR 0x01
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#define TRANSMIT_COLLISION 0x04
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#define TRANSMIT_ABORT 0x08
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#define TRANSMIT_LOST_CARRIER 0x10
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#define TRANSMIT_FIFO_UNDERRUN 0x20
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#define TRANSMIT_HEARTBEAT 0x40
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#define TRANSMIT_OUT_OF_WINDOW 0x80
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//
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// RECEIVE_CONFIG_REG
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//
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#define SAVE_ERROR_PACKETS 0x01
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#define SAVE_RUNT_PACKETS 0x02
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#define SAVE_BROADCAST_PACKETS 0x04
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#define SAVE_MULTICAST_PACKETS 0x08
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#define PROMISCUOUS_MODE 0x10
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#define MONITOR_MODE 0x20
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//
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// RECEIVE_STATUS_REG
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#define RECEIVE_NO_ERROR 0x01
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#define RECEIVE_CRC_ERROR 0x02
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#define RECEIVE_ALIGNMENT_ERROR 0x04
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#define RECEIVE_FIFO_UNDERRUN 0x08
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#define RECEIVE_MISSED_PACKET 0x10
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#define RECEIVE_PHYSICAL_ADDRESS 0x20
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#define RECEIVE_DISABLED 0x40
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#define RECEIVE_DEFERRING 0x80
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