488 lines
13 KiB
C
488 lines
13 KiB
C
/*++
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Copyright (c) 1994 NeTpower, Inc.
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Copyright (c) 1992 Pellucid, inc.
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Module Name:
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hm.h
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Abstract:
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Hm board register definitions.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef __HM_H__
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#define __HM_H__
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//
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// Addresses used for accessing hardware.
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//
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#define PEL_GFX1_PBASE 0x40000000
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#define PEL_GFX1_SIZE 0x01100000
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//
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// Define for write buffer flushing.
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//
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#define FLUSHIO()
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//
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// Cursor chip registers.
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//
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typedef struct
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{
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volatile ULONG jAddressLo; // Address low
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volatile ULONG jAddressHi; // Address high
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volatile ULONG jGlyph; // Glyph data
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volatile ULONG jControl; // Control
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}
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CURSOR, * PCURSOR;
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//
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// Control register offsets.
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//
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#define CURS_CMD 0
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#define CURS_XLO 1
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#define CURS_XHI 2
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#define CURS_YLO 3
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#define CURS_YHI 4
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#define CURS_WINXLO 5
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#define CURS_WINXHI 6
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#define CURS_WINYLO 7
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#define CURS_WINYHI 8
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#define CURS_WINWLO 9
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#define CURS_WINWHI 10
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#define CURS_WINHLO 11
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#define CURS_WINHHI 12
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//
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// Cursor chip commands.
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//
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#define CURS_BLOCK 0x40
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#define CURS_CROSS 0x20
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#define CURS_FMT 0x01
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#define CURS_1TO1MUX 0x00
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#define CURS_4TO1MUX 0x04
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#define CURS_5TO1MUX 0x08
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//
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// Cursor offsets for different monitor types.
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//
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#define CURS_XHOTOFF 31
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#define CURS_YHOTOFF 32
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#define CURS_XOFF_60HZ 221
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#define CURS_YOFF_60HZ 998
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#define CURS_XOFF_30HZ 39
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#define CURS_YOFF_30HZ 18
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#define CURS_XOFF_NTSC 25
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#define CURS_YOFF_NTSC 437
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#define CURS_XOFF_PAL 57
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#define CURS_YOFF_PAL 535
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//
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// RAMDAC registers.
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//
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typedef struct
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{
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volatile ULONG jRamDacAddress; // RAMDAC address;
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volatile ULONG jPalette; // Color palette RAM
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volatile ULONG jData; // Data register for RAMDAC address
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volatile ULONG jOverlayPalette; // Overlay palette RAM
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}
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RAMDAC, * PRAMDAC;
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//
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// RAMDAC definitions.
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//
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#define DAC_READMASK 0x04
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#define DAC_BLINKMASK 0x05
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#define DAC_CMD 0x06
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#define DAC_TEST 0x07
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//
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// DAC command bit definitions.
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//
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#define DAC_5TO1MUX 0x80
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#define DAC_PALENABLE 0x40
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#define DAC_BLINK0 0x00
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#define DAC_BLINK1 0x10
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#define DAC_BLINK2 0x20
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#define DAC_BLINK3 0x30
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#define DAC_OL1BLINKENABLE 0x08
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#define DAC_OL0BLINKENABLE 0x04
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#define DAC_OL1ENABLE 0x02
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#define DAC_OL0ENABLE 0x01
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#define CURSOR_WIDTH 32
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#define CURSOR_HEIGHT 32
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#define CURSOR_MAXIMUM ((CURSOR_WIDTH / 8) * CURSOR_HEIGHT)
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//
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// Offsets within the graphics space.
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//
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#define HM_RGB_LINEAR 0x00000000
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#define HM_REG_OFF 0x01000000
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#define HM_RGB_Y0 (HM_REG_OFF + 0x00000000)
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#define HM_RGB_Y1 (HM_REG_OFF + 0x00010000)
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#define HM_BLK_Y0 (HM_REG_OFF + 0x00020000)
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#define HM_BLK_Y1 (HM_REG_OFF + 0x00030000)
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#define HM_BLTLOAD_Y0 (HM_REG_OFF + 0x00040000)
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#define HM_BLTLOAD_Y1 (HM_REG_OFF + 0x00050000)
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#define HM_BLTSTORE_Y0 (HM_REG_OFF + 0x00060000)
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#define HM_BLTSTORE_Y1 (HM_REG_OFF + 0x00070000)
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#define HM_BT457 (HM_REG_OFF + 0x00080000)
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#define HM_BT431 (HM_REG_OFF + 0x00090000)
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#define HM_COLOR (HM_REG_OFF + 0x000A0000)
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#define HM_WRITEMASK (HM_REG_OFF + 0x000B0000)
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#define HM_Y0 (HM_REG_OFF + 0x000C0000)
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#define HM_Y1 (HM_REG_OFF + 0x000C0004)
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#define HM_GENERAL (HM_REG_OFF + 0x000D0000)
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#define HM_VIDTIM (HM_REG_OFF + 0x000E0000)
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#define HM_CLRINTR (HM_REG_OFF + 0x000F0000)
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// general control/status bit assignments
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#define G_REDLANE 0x00000003
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#define G_GRNLANE 0x0000000C
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#define G_BLULANE 0x00000030
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#define G_MODE1280 0x00000040 /* 1=1280/1024, 0=1024/768 */
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#define G_FASTREF 0x00000080 /* always 0 */
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#define G_MASKVINTR 0x00000100 /* 0=vertical retrace intr enabled */
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#define G_VGAPASS 0x00000200 /* 1 = VGA passthrough enabled */
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#define G_RST439 0x00000400 /* 0 = reset BT439 chip */
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#define G_SYNCPOL 0x00000800 /* 0 = active high, 1 = active low */
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#define G_UCTRL2 0x00001000 /* unused */
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#define G_SEL1 0x00002000 /* ICD2062 SEL1 pin */
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#define G_SEL0 0x00004000 /* ICD2062 SEL0 pin */
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#define G_NOSYNCGRN 0x00008000 /* 1 = disable sync on green channel */
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#define G_BLKSENSE 0x00010000 /* ??? */
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#define G_WAIT2 0x00020000 /* 1 = 0 wait states */
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#define G_WAIT3 0x00040000 /* 1 = 1 wait state */
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#define G_IRQSEL1 0x00080000 /* IRQSEL[1:0] 11 = IRQ 7 10 = IRQ 11
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#define G_IRQSEL0 0x00100000 /* 01 = IRQ 10 00 = IRQ 9(2)
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#define G_RAWINTR 0x00200000 /* raw value of vertical interrupt */
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#define G_USTAT1 0x00400000 /* unused */
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#define G_USTAT0 0x00800000 /* ICD2062 ERR* pin */
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//
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// Define the write-only Control Port (Port 1) bits.
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//
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#define CP_PORT_EN 0x01 // Port enable - enable this port if = 1.
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#define CP_HUE_EN 0x02 // HUE-1 enable - enable the HUE ASIC if = 1.
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#define CP_NVRAM_CLK 0x04 // NVRAM clock (sk) signal.
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#define CP_NVRAM_EN 0x08 // NVRAM enable (cs) signal.
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#define CP_NVRAM_DATA 0x10 // NVRAM data out (do) signal.
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#define CP_HIRES_EN 0x20 // Hi-Resolution enable - goto hires if = 1.
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//
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// Define the read-only Status Port (Port 0 or 1) bits.
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//
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#define SP_SIGNATURE_MASK 0x0F // Signature mask.
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#define SP_SIGNATURE 0x0A // Signature (4 bits).
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#define SP_NVRAM_DATA 0x10 // NVRAM di (data in) signal.
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#define SP_HIRES_EN 0x20 // Hi-resolution enable - goto hires if = 1.
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#define SP_PORT_SEL_MASK 0xC0 // I/O port select lines
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#define SP_PORT_SEL_0 0x00 // 00 = Port Choice 0 = 0538h-0539h.
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#define SP_PORT_SEL_1 0x40 // 40 = Port Choice 1 = 0E88h-0E89h.
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#define SP_PORT_SEL_2 0x80 // 80 = Port Choice 2 = 0F48h-0F49h.
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#define SP_PORT_SEL_3 0xC0 // C0 = Port Choice 3 = 060Ch-060Dh.
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//
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// Define device extension structure.
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//
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typedef struct _HW_DEVICE_EXTENSION
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{
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PHYSICAL_ADDRESS PhysicalGraphicsAddress0;
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ULONG GraphicsLength0;
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USHORT HorizontalResolution;
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USHORT HorizontalScreenSize;
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USHORT VerticalResolution;
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USHORT VerticalScreenSize;
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ULONG fxVBase;
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ULONG NumAvailableModes;
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ULONG iCurrentMode;
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PVOID VideoAddress;
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}
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HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
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//
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// This is the mode structure definitions.
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//
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// temporary - 3/9/93 - roey - used to hardcode certain values
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#define HM_GFX_IRQ 11 // vertical retrace IRQ
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#define HM_GFX_IRQ_SEL G_IRQSEL1 // GENERAL REG IRQ select lines
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// IRQ 11 : sel1 = 1, sel0 = 0
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#define HM_MAPPING_PORT ((PUCHAR)0x538) // The framebuffer mapping I/O port.
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#define HM_CONTROL_PORT ((PUCHAR)0x539) // The control I/O port.
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typedef struct _VIDEO_MODE_INFORMATION {
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ULONG Length;
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ULONG ModeIndex;
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ULONG VisScreenWidth;
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ULONG VisScreenHeight;
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ULONG ScreenStride;
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ULONG NumberOfPlanes;
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ULONG BitsPerPlane;
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ULONG Frequency;
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ULONG XMillimeter;
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ULONG YMillimeter;
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ULONG NumberRedBits;
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ULONG NumberGreenBits;
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ULONG NumberBlueBits;
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ULONG RedMask;
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ULONG GreenMask;
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ULONG BlueMask;
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ULONG AttributeFlags;
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ULONG VideoMemoryBitmapWidth;
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ULONG VideoMemoryBitmapHeight;
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} VIDEO_MODE_INFORMATION, *PVIDEO_MODE_INFORMATION;
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typedef struct {
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ULONG mClkData,
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vClkData;
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} MVPG_ICD2062;
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typedef MVPG_ICD2062 *PMVPG_ICD2062;
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typedef struct {
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ULONG hBlankOn,
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hBlankOff,
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hSyncOn,
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hSyncOff,
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vBlankOn,
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vBlankOff,
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vSyncOn,
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vSyncOff;
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} MVPG_TIMINGS;
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typedef MVPG_TIMINGS *PMVPG_TIMINGS;
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typedef struct {
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UCHAR szModeName[32];
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VIDEO_MODE_INFORMATION VideoModeInformation;
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MVPG_TIMINGS mvpgTimings;
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MVPG_ICD2062 mvpgIcd2062;
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ULONG mvpgGeneralRegister;
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ULONG Bt457CommandReg;
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} MVPG_MODE;
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typedef MVPG_MODE *PMVPG_MODE;
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BOOLEAN HmInitHw(PHW_DEVICE_EXTENSION);
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VOID VideoTiming(PHW_DEVICE_EXTENSION, ULONG, ULONG, ULONG, ULONG, ULONG, ULONG, ULONG, ULONG);
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VOID InitHM(PHW_DEVICE_EXTENSION);
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VOID ResetBT439(PHW_DEVICE_EXTENSION);
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VOID Write_BT457(PHW_DEVICE_EXTENSION, ULONG, ULONG);
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VOID InitBT457(PHW_DEVICE_EXTENSION);
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VOID ProgramICD2062(PHW_DEVICE_EXTENSION, ULONG, ULONG);
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/***************************************************************************
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*
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* NeTpower NeTgraphics 1280 mode tables.
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*
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* Created:
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* August 27, 1993 -by- Jeffrey Newman (NewCon)
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*
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* Copyright (c) Newman Consulting 1993
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* Copyright (c) Media Vision 1993
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***************************************************************************/
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MVPG_MODE aMvpgModes[] = {
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{
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{"1280X1024X32bpp@60Hz"},
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{ sizeof(VIDEO_MODE_INFORMATION),
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0,
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1280,
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1024,
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2048 * 4,
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1,
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32,
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60,
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800,
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600,
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8,
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8,
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8,
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0xFF0000,
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0x00FF00,
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0x0000FF,
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#if 1
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0,
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#else
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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#endif
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1280,
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1024
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},
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{
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253,
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333,
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269,
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291,
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1023,
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1066,
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1024,
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1029
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},
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{
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0x000f71a0 | (3 << 21),
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0x00183002
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},
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{
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0x06 | // Define byte lanes as RGB, from LSB to MSB.
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G_MODE1280 | // Select 1280x1024 mode.
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G_MASKVINTR | // Mask off the vertical retrace interrupt.
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G_RST439 | // Stop resetting the BT439 chip.
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G_SYNCPOL | // Sync polarity is active low.
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G_WAIT3 | // Select 0 wait states.
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G_NOSYNCGRN | // Disable sync on green channel.
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HM_GFX_IRQ_SEL // Select vertical retrace IRQ.
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},
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{
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0xC0C0C0
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}
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},
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{
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{"1024X768X32bpp@60Hz"},
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{ sizeof(VIDEO_MODE_INFORMATION),
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1,
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1024,
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768,
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2048 * 4,
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1,
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32,
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60,
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800,
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600,
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8,
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8,
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8,
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0xFF0000,
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0x00FF00,
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0x0000FF,
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#if 1
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0,
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#else
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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#endif
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1024,
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768
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},
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{
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253,
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330,
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268,
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294,
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768,
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805,
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770,
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776
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},
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{
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0x000f71a0 | (3 << 21),
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0x00068c0f
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},
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{
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0x06 | // Define byte lanes as RGB, from LSB to MSB.
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G_MASKVINTR | // Mask off the vertical retrace interrupt.
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G_RST439 | // Stop resetting the BT439 chip.
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G_SYNCPOL | // Sync polarity is active low.
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G_WAIT3 | // Select 0 wait states.
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G_NOSYNCGRN | // Disable sync on green channel.
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HM_GFX_IRQ_SEL // Select vertical retrace IRQ.
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},
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{
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0x404040
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}
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},
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{
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// This is a special debug mode that returns a 1024 mode
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// to the display driver, but really sets the chip to 1280 mode.
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{"1024X768X32bpp@70Hz"},
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{ sizeof(VIDEO_MODE_INFORMATION),
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2,
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1024,
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768,
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2048 * 4,
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1,
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32,
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70,
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800,
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600,
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8,
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8,
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8,
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0xFF0000,
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0x00FF00,
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0x0000FF,
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#if 1
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0,
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#else
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS,
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#endif
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1024,
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768
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},
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{
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253,
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333,
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269,
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291,
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1023,
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1066,
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1024,
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1029
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},
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{
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0x000f71a0 | (3 << 21),
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0x00183002
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},
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{
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0x06 | // Define byte lanes as RGB, from LSB to MSB.
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G_MODE1280 | // Select 1280x1024 mode.
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G_MASKVINTR | // Mask off the vertical retrace interrupt.
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G_RST439 | // Stop resetting the BT439 chip.
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G_SYNCPOL | // Sync polarity is active low.
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G_WAIT3 | // Select 0 wait states.
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G_NOSYNCGRN | // Disable sync on green channel.
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HM_GFX_IRQ_SEL // Select vertical retrace IRQ.
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},
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{
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0xC0C0C0
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}
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}
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};
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#endif // __HM_H__
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