343 lines
10 KiB
C
343 lines
10 KiB
C
/*++
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Copyright (c) 1993, NeTpower, Inc. All rights reserved.
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Module Name:
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vga.h
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Abstract:
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Standard VGA support header file. Everything needed to initialize,
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and talk to standard VGA cards on either the PICA or the ISA bus.
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Reference: Programmers Guide to the EGA and VGA, Second Edition.
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by Richard F. Ferraro. ISBN 0-201-57025-4, 1990.
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Author:
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Mike Dove (mdove), 8-Oct-93
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--*/
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#ifndef _VGA_
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#define _VGA_
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//
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// Set up typedef's for the VGA ports. Depending on whether you are
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// reading or writing, some of the registers appear at different addresses.
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// Therefore, there are two typedef structures defined depending on
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// whether you are doing reads or writes... These registers start at
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// offset 0x3C0.
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//
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typedef volatile struct _VGA_READ_PORT {
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/* 000 */ UCHAR None_0[0x102];
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/* 102 */ UCHAR SetupOptionSelect; // S3 only...
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/* 103 */ UCHAR None_1[0x2be];
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/* 3C1 */ UCHAR AttributeAddressAndData;
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/* 3C2 */ UCHAR InputStatus0;
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/* 3C3 */ UCHAR None_2;
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/* 3C4 */ UCHAR SequencerAddress;
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/* 3C5 */ UCHAR SequencerData;
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/* 3C6 */ UCHAR PELMask;
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/* 3C7 */ UCHAR DACState;
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/* 3C8 */ UCHAR PELAddressWriteMode;
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/* 3C9 */ UCHAR PELData;
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/* 3CA */ UCHAR FeatureControl;
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/* 3CB */ UCHAR None_3;
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/* 3CC */ UCHAR MiscOutput;
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/* 3CD */ UCHAR None_4;
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/* 3CE */ UCHAR GraphicsAddress;
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/* 3CF */ UCHAR GraphicsData;
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/* 3D0 */ UCHAR None_5[4];
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/* 3D4 */ UCHAR CRTCAddress;
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/* 3D5 */ UCHAR CRTCData;
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/* 3D6 */ UCHAR None_6[4];
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/* 3DA */ UCHAR InputStatus1;
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} VGA_READ_PORT, *PVGA_READ_PORT;
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typedef volatile struct _VGA_WRITE_PORT {
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/* 000 */ UCHAR None_0[0x102];
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/* 102 */ UCHAR SetupOptionSelect; // S3 only...
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/* 103 */ UCHAR None_1[0x2bd];
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/* 3C0 */ UCHAR AttributeAddressAndData;
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/* 3C1 */ UCHAR None_2;
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/* 3C2 */ UCHAR MiscOutput;
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/* 3C3 */ UCHAR None_3;
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/* 3C4 */ UCHAR SequencerAddress;
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/* 3C5 */ UCHAR SequencerData;
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/* 3C6 */ UCHAR PELMask;
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/* 3C7 */ UCHAR PELAddressReadMode;
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/* 3C8 */ UCHAR PELAddressWriteMode;
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/* 3C9 */ UCHAR PELData;
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/* 3CA */ UCHAR None_4[4];
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/* 3CE */ UCHAR GraphicsAddress;
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/* 3CF */ UCHAR GraphicsData;
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/* 3D0 */ UCHAR None_5[4];
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/* 3D4 */ UCHAR CRTCAddress;
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/* 3D5 */ UCHAR CRTCData;
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/* 3D6 */ UCHAR None_6[4];
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/* 3DA */ UCHAR FeatureControl;
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/* 3DB */ UCHAR None_7[0x3f0d];
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/* 42E8 */ USHORT SubsystemControlRegister; // S3 only...
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/* 42E9 */ UCHAR None_8[0x3fe];
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/* 46E8 */ UCHAR VideoSubsystemEnable; // S3 only...
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/* 46E9 */ UCHAR None_9[0x3ff];
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/* 4AE8 */ USHORT AdvancedFunctionControl; // S3 only...
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} VGA_WRITE_PORT, *PVGA_WRITE_PORT;
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//
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// The following #defines represent the indexes used for the Address/Data
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// register sets. The data for the *Setup arrays was taken from pages 318-319
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// in the Programmers Guide to the EGA and VGA for video mode 3.
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//
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// Sequencer Registers
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#define SEQ_RESET 0
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#define SYNCHRONUS_RESET 0x01
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#define NORMAL_OPERATION 0x03
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#define SEQ_CLOCKING_MODE 1
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#define SEQ_MAP_MASK 2
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#define ENABLE_PLANE_2 0x04
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#define SEQ_CHARACTER_MAP_SELECT 3
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#define SEQ_MEMORY_MODE 4
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#define SEQUENTIAL_ADDRESSING 0x04
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#define EXTENDED_MEMORY 0x02
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static UCHAR SequencerSetup[] = {
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0x03, // Reset
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0x00, // Clocking Mode
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0x03, // Map Mask
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0x00, // Character Map Select
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0x02, // Memory Mode
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};
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// CRT Controller Registers
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#define CRT_HORIZONTAL_TOTAL 0
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#define CRT_HORIZONTAL_DISPLAY_END 1
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#define CRT_START_HORIZONTAL_BLANKING 2
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#define CRT_END_HORIZONTAL_BLANKING 3
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#define CRT_START_HORIZONTAL_RETRACE 4
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#define CRT_END_HORIZONTAL_RETRACE 5
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#define CRT_VERTICAL_TOTAL 6
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#define CRT_OVERFLOW 7
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#define CRT_PRESET_ROW_SCAN 8
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#define CRT_MAXIMUM_SCAN_LINE 9
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#define CRT_CURSOR_START 10
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#define CRT_CURSOR_END 11
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#define CRT_START_ADDRESS_HIGH 12
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#define CRT_START_ADDRESS_LOW 13
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#define CRT_CURSOR_LOCATION_HIGH 14
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#define CRT_CURSOR_LOCATION_LOW 15
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#define CRT_VERTICAL_RETRACE_START 16
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#define CRT_VERTICAL_RETRACE_END 17
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#define CRT_VERTICAL_DISPLAY_END 18
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#define CRT_OFFSET 19
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#define CRT_UNDERLINE_LOCATION 20
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#define CRT_START_VERTICAL_BLANK 21
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#define CRT_END_VERTICAL_BLANK 22
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#define CRT_MODE_CONTROL 23
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#define CRT_LINE_COMPARE 24
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static UCHAR CRTCSetup[] = {
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0x5f, // Horizontal Total
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0x4f, // Horizontal Display End
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0x50, // Start Horizontal Blanking
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0x82, // End Horizontal Blanking
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0x55, // Start Horizontal Retrace
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0x81, // End Horizontal Retrace
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0xbf, // Vertical Total
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0x1f, // Overflow
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0x00, // Preset Row Scan
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0x4b, // Maximum Scan Line - Changes: 2T4 turned off, 12 row characters
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0x0e, // Cursor Start - Changes: 16 row characters, move cursor down
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0x0f, // Cursor End - Changes: 16 row characters, move cursor down
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0x00, // Start Address High
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0x00, // Start Address Low
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0x00, // Cursor Location High
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0x00, // Cursor Location Low - Changes: Start at 0
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0x9c, // Vertical Retrace Start
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0x8e, // Vertical Retrace End - also write protects CRT registers 0-7.
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0x8f, // Vertical Display End
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0x28, // Offset
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0x1f, // Underline Location
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0x96, // Start Vertical Blank
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0xb9, // End Vertical Blank
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0xa3, // Mode Control
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0xff, // Line Compare
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};
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// Graphics Registers
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#define GFX_SET_RESET 0
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#define GFX_ENABLE_SET_RESET 1
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#define GFX_COLOR_COMPARE 2
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#define GFX_DATA_ROTATE 3
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#define GFX_READ_MAP_SELECT 4
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#define GFX_MODE 5
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#define WRITE_MODE_0 0x00
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#define GFX_MISCELLANEOUS 6
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#define MEMORY_MODE_1 0x04
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#define ALPHA_MODE 0x00
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#define GFX_COLOR_DONT_CARE 7
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#define GFX_BIT_MASK 8
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static UCHAR GraphicsSetup[] = {
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0x00, // Set/Reset
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0x00, // Enable Set/Reset
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0x00, // Color Compare
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0x00, // Data Rotate
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0x00, // Read Map Select
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0x10, // Mode
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0x0e, // Miscellaneous
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0x00, // Color Don't Care
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0xff, // Bit Mask
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};
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// Attribute Registers
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#define ATT_PALETTE_00 0
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#define ATT_PALETTE_01 1
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#define ATT_PALETTE_02 2
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#define ATT_PALETTE_03 3
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#define ATT_PALETTE_04 4
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#define ATT_PALETTE_05 5
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#define ATT_PALETTE_06 6
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#define ATT_PALETTE_07 7
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#define ATT_PALETTE_08 8
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#define ATT_PALETTE_09 9
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#define ATT_PALETTE_10 10
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#define ATT_PALETTE_11 11
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#define ATT_PALETTE_12 12
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#define ATT_PALETTE_13 13
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#define ATT_PALETTE_14 14
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#define ATT_PALETTE_15 15
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#define ATT_MODE 16
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#define ATT_OVERSCAN_COLOR 17
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#define ATT_COLOR_PLANE_ENABLE 18
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#define ATT_HORIZONTAL_PIXEL_PANNING 19
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#define ATT_COLOR_SELECT 20
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static UCHAR AttributeSetup[] = {
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0x00, // Palette 00 Index - Black
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0x01, // Palette 01 Index - Red
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0x02, // Palette 02 Index - Green
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0x03, // Palette 03 Index - Yellow
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0x04, // Palette 04 Index - Blue
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0x05, // Palette 05 Index - Magenta
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0x06, // Palette 06 Index - Cyan
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0x07, // Palette 07 Index - White
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0x08, // Palette 08 Index - Intense Black (read Grey)
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0x09, // Palette 09 Index - Intense Red
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0x0a, // Palette 10 Index - Intense Green
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0x0b, // Palette 11 Index - Intense Yellow
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0x0c, // Palette 12 Index - Intense Blue
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0x0d, // Palette 13 Index - Intense Magenta
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0x0e, // Palette 14 Index - Intense Cyan
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0x0f, // Palette 15 Index - Intense White
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0x04, // Mode
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0x00, // Overscan Color
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0x0F, // Color Plane Enable
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0x08, // Horizontal Pixel Panning
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0x00, // Color Select
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};
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static UCHAR ColorValues[16][3] = {
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// Red Grn Blue
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00, 00, 00, // Black
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42, 00, 00, // Red
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00, 42, 00, // Green
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42, 21, 00, // Brown
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00, 00, 42, // Blue
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42, 00, 42, // Magenta
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00, 42, 42, // Cyan
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42, 42, 42, // White
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21, 21, 21, // Intense Black (read Grey)
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63, 21, 21, // Intense Red
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21, 63, 21, // Intense Green
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63, 63, 21, // Intense Brown
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21, 21, 63, // Intense Blue
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63, 21, 63, // Intense Magenta
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21, 63, 63, // Intense Cyan
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63, 63, 63, // Intense White
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};
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#define COLOR_BLACK 0
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#define COLOR_RED 1
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#define COLOR_GREEN 2
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#define COLOR_BROWN 3
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#define COLOR_BLUE 4
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#define COLOR_MAGENTA 5
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#define COLOR_CYAN 6
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#define COLOR_WHITE 7
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#define COLOR_GREY 8
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#define COLOR_INTENSE_RED 9
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#define COLOR_INTENSE_GREEN 10
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#define COLOR_INTENSE_BROWN 11
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#define COLOR_INTENSE_BLUE 12
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#define COLOR_INTENSE_MAGENTA 13
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#define COLOR_INTENSE_CYAN 14
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#define COLOR_INTENSE_WHITE 15
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// Other register bit definitions...
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// Miscellaneous Output Register
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#define IOA_COLOR 0x01
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#define ER_ENABLE 0x02
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#define CS_25MHZ 0x00
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#define CS_28MHZ 0x04
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#define CS_ENHANCED 0x06
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#define DVD_ENABLE 0x00
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#define PB_HIGH64K 0x20
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#define HSP_NEGATIVE 0x40
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#define VSP_POSITIVE 0x00
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#define VSP_NEGATIVE 0x80
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#define INITIAL_CONFIG ( IOA_COLOR \
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| ER_ENABLE \
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| CS_ENHANCED \
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| DVD_ENABLE \
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| PB_HIGH64K \
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| HSP_NEGATIVE \
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| VSP_POSITIVE \
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)
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// S3 specific #defines
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#define ENTER_SETUP_MODE 0x10
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#define ENABLE_VIDEO_SUBSYSTEM 0x08
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#define VIDEO_SUBSYSTEM_ALIVE 0x01
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#define S3_CHIP_ID 0x30
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#define S3_MEMORY_CONFIGURATION 0x31
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#define S3_BACKWARD_COMPATIBILITY_1 0x32
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#define S3_BACKWARD_COMPATIBILITY_2 0x33
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#define S3_BACKWARD_COMPATIBILITY_3 0x34
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#define S3_CRT_REGISTER_LOCK 0x35
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#define S3_CONFIGURATION_1 0x36
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#define S3_CONFIGURATION_2 0x37
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#define S3_REGISTER_LOCK_1 0x38
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#define S3_REGISTER_LOCK_2 0x39
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#define S3_MISCELLANEOUS_1 0x3a
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#define S3_DATA_TRANSFER_EXECUTE 0x3b
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#define S3_INTERLACE_RETRACE_START 0x3c
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#define S3_SYSTEM_CONFIGURATION 0x40
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#define S3_MODE_CONTROL 0x42
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#define S3_EXTENDED_MODE 0x43
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#define S3_HARDWARE_GRAPHICS_CURSOR 0x45
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#define S3_EXTENDED_MEMORY_CONTROL_1 0x53
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#define S3_EXTENDED_MEMORY_CONTROL_2 0x54
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#define S3_LINEAR_ADDRESS_WINDOW_HIGH 0x59
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#define S3_LINEAR_ADDRESS_WINDOW_LOW 0x5A
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// Other #defines
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#define SPACE 0x20 // Ascii space
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#endif
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