171 lines
5.8 KiB
C
171 lines
5.8 KiB
C
/*++
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Copyright (c) 1993 Microsoft Corporation
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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pintolin.h
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Abstract:
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This file includes the platform-dependent Pin To Line Tables
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Author:
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Steve Brooks 6-July 1994
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Environment:
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Kernel mode
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Revision History:
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--*/
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//
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// These tables represent the mapping from slot number and interrupt pin
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// into a PCI Interrupt Vector.
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//
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// Formally, these mappings can be expressed as:
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//
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// PCIPinToLine:
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// SlotNumber.DeviceNumber x InterruptPin -> InterruptLine
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//
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// LineToVector:
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// InterruptLine -> InterruptVector
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//
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// VectorToIRRBit:
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// InterruptVector -> InterruptRequestRegisterBit
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//
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// VectorToIMRBit:
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// InterruptVector -> InterruptMaskRegisterBit
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//
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// SlotNumberToIDSEL:
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// SlotNumber.DeviceNumber -> IDSEL
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//
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// subject to following invariants (predicates must always be true):
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//
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// Slot.DeviceNumber in {0,...,15}
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//
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// InterruptPin in {1, 2, 3, 4}
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//
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// InterruptRequestRegisterBit in {0,...,15}
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//
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// InterruptMaskRegisterBit in {0,...,15}
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//
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// PCIPinToLine(SlotNumber.DeviceNumber, InterruptPin) =
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// PCIPinToLineTable[SlotNumber.DeviceNumber, InterruptPin]
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// (Table-lookup function initialized below)
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//
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// LineToVector(InterruptLine) = PCI_VECTORS + InterruptLine
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//
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// VectorToIRRBit(InterruptVector) = InterruptVector - 1
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//
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// VectorToIMRBit(InterruptVector) [see below]
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//
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// SlotNumberToIDSEL(SlotNumber.DeviceNumber) = (1 << (Slot.DeviceNumber+11))
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//
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// where:
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//
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// SlotNumber.DeviceNumber:
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// Alpha AXP Platforms receive interrupts on local PCI buses only, which
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// are limited to 16 devices (PCI AD[11]-AD[26]). (We loose AD[27]-AD[31]
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// since PCI Config space is a sparse space, requiring a five-bit shift.)
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//
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// InterruptPin:
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// Each virtual slot has up to four interrupt pins INTA#, INTB#, INTC#, INTD#,
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// as per the PCI Spec. V2.0, Section 2.2.6. (FYI, only multifunction devices
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// use INTB#, INTC#, INTD#.)
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//
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// PCI configuration space indicates which interrupt pin a device will use
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// in the InterruptPin register, which has the values:
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//
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// INTA# = 1, INTB#=2, INTC#=3, INTD# = 4
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//
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// Note that there may be up to 8 functions/device on a PCI multifunction
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// device plugged into the option slots, e.g., Slot #0.
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// Each function has it's own PCI configuration space, addressed
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// by the SlotNumber.FunctionNumber field, and will identify which
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// interrput pin of the four it will use in it's own InterruptPin register.
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//
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// If the option is a PCI-PCI bridge, interrupts across the bridge will
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// somehow be combined to appear on some combination of the four
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// interrupt pins that the bridge plugs into.
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//
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// InterruptLine:
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// This PCI Configuration register, unlike x86 PC's, is maintained by
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// software and represents offset into PCI interrupt vectors.
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// Whenever HalGetBusData or HalGetBusDataByOffset is called,
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// HalpPCIPinToLine() computes the correct InterruptLine register value
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// by using the HalpPCIPinToLineTable mapping.
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//
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// InterruptRequestRegisterBit:
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// 0xff is used to mark an invalid IRR bit, hence an invalid request
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// for a vector. Also, note that the 16 bits of the EB66 IRR must
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// be access as two 8-bit reads.
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//
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// InterruptMaskRegisterBit:
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// On EB66, the PinToLine table may also be find the to write the
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// InterruptMaskRegister. Formally, we can express this invariant as
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//
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// VectorToIMRBit(InterrruptVector) = InterruptVector - 1
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//
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//
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// IDSEL:
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// For accessing PCI configuration space on a local PCI bus (as opposed
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// to over a PCI-PCI bridge), type 0 configuration cycles must be generated.
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// In this case, the IDSEL pin of the device to be accessed is tied to one
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// of the PCI Address lines AD[11] - AD[26]. (The function field in the
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// PCI address is used should we be accessing a multifunction device.)
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// Anyway, virtual slot 0 represents the device with IDSEL = AD[11], and
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// so on.
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//
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//
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// Interrupt Vector Table Mapping for Alcor.
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//
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// Alcor PCI interrupts are mapped to arbitrary interrupt numbers
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// in the table below. The values are a 1-1 map of the bit numbers
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// in the Alcor PCI interrupt register that are connected to PCI
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// devices. N.B.: there are two other interrupts in this register,
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// but they are not connected to I/O devices, so they're not
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// represented in the table.
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//
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// Limit init table to 14 entries, which is the
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// MAX_PCI_LOCAL_DEVICES_MIKASA.
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//
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// We won't ever try to set an InterruptLine register of a slot
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// greater than Virtual slot 13 = PCI_AD[24].
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//
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//
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// N.B. - Have biased the bus interrupt vectors/levels for PCI to start
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// at 0x11 so they are disjoint from EISA levels
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//
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ULONG *HalpPCIPinToLineTable;
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ULONG AlcorPCIPinToLineTable[][4]=
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{
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//
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// Pin 1 Pin 2 Pin 3 Pin 4
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// ----- ----- ----- -----
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//
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 0 = PCI_AD[11]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 1 = PCI_AD[12]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 2 = PCI_AD[13]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 3 = PCI_AD[14]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 4 = PCI_AD[15]
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 5 = PCI_AD[16]
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{ 0x1e, 0xff, 0xff, 0xff }, // Virtual Slot 6 = PCI_AD[17] Maverick Ethernet Controller
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{ 0x19, 0x1a, 0x1b, 0x1c }, // Virtual Slot 7 = PCI_AD[18] 64 bit Slot #0
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{ 0x21, 0x22, 0x23, 0x24 }, // Virtual Slot 8 = PCI_AD[19] 32 bit Slot #0
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{ 0x1d, 0x1e, 0x1f, 0x20 }, // Virtual Slot 9 = PCI_AD[20] 32 bit Slot #1
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{ 0xff, 0xff, 0xff, 0xff }, // Virtual Slot 10 = PCI_AD[21] Eisa Bridge
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{ 0x11, 0x12, 0x13, 0x14 }, // Virtual Slot 11 = PCI_AD[22] 64 bit Slot #2
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{ 0x15, 0x16, 0x17, 0x18 }, // Virtual Slot 12 = PCI_AD[23] 64 bit Slot #1
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};
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