338 lines
7.5 KiB
C
338 lines
7.5 KiB
C
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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apecs.c
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Abstract:
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This module implements functions that are specific to the APECS
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chip-set.
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Author:
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Joe Notarangelo 18-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "apecs.h"
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VOID
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DumpEpic(
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VOID
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);
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//
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// Globals
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//
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//
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// Parity checking is a tri-state variable, unknown == all f's. Which means
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// Keep checking disabled until we can determine what we want to set it to,
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// which then means 1 or 0.
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//
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extern ULONG HalDisablePCIParityChecking;
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VOID
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HalpApecsInitializeSfwWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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APECS_WINDOW_NUMBER WindowNumber
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)
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/*++
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Routine Description:
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Initialize the DMA Control software window registers for the specified
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DMA Window.
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Arguments:
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WindowRegisters - Supplies a pointer to the software window control.
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WindowNumber - Supplies the window number initialized. (0 = Isa Dma
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Window, 1 = Master Dma Window).
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Return Value:
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None.
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--*/
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{
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switch( WindowNumber ){
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//
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// The ISA DMA Window.
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//
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case ApecsIsaWindow:
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WindowRegisters->WindowBase = (PVOID)ISA_DMA_WINDOW_BASE;
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WindowRegisters->WindowSize = ISA_DMA_WINDOW_SIZE;
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WindowRegisters->TranslatedBaseRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TranslatedBase1Register;
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WindowRegisters->WindowBaseRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciBase1Register;
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WindowRegisters->WindowMaskRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciMask1Register;
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WindowRegisters->WindowTbiaRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TbiaRegister;
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break;
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case ApecsMasterWindow:
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WindowRegisters->WindowBase = (PVOID)MASTER_DMA_WINDOW_BASE;
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WindowRegisters->WindowSize = MASTER_DMA_WINDOW_SIZE;
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WindowRegisters->TranslatedBaseRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TranslatedBase2Register;
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WindowRegisters->WindowBaseRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciBase2Register;
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WindowRegisters->WindowMaskRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciMask2Register;
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WindowRegisters->WindowTbiaRegister =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TbiaRegister;
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break;
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default:
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#if DBG
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DbgPrint( "ApecsInitializeSfwWindow: Bad Window Number = %x\n",
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WindowNumber );
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#endif //DBG
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break;
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}
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return;
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}
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VOID
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HalpApecsProgramDmaWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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PVOID MapRegisterBase
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)
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/*++
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Routine Description:
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Program the control windows in the hardware so that DMA can be started
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to the DMA window.
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Arguments:
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WindowRegisters - Supplies a pointer to the software window register
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control structure.
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MapRegisterBase - Supplies the logical address of the scatter/gather
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array in system memory.
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Return Value:
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None.
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--*/
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{
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EPIC_ECSR Ecsr;
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EPIC_PCIBASE PciBase;
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EPIC_PCIMASK PciMask;
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EPIC_TBASE TBase;
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PVOID RegisterQva;
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PciBase.Reserved = 0;
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PciBase.Wenr = 1;
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PciBase.Sgen = 1;
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PciBase.BaseValue = (ULONG)(WindowRegisters->WindowBase) >> 20;
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PciMask.Reserved = 0;
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PciMask.MaskValue = (WindowRegisters->WindowSize >> 20) - 1;
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TBase.Reserved = 0;
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TBase.TBase = (ULONG)(MapRegisterBase) >> 10;
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#if DBG
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//
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// Dump the EPIC registers.
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//
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DumpEpic();
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#endif //DBG
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//
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// Clear the window base, temporarily disabling transactions to this
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// DMA window.
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//
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WRITE_EPIC_REGISTER( WindowRegisters->WindowBaseRegister, (ULONG)0 );
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//
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// Now program the window by writing the translated base, then the size
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// of the window in the mask register and finally the window base,
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// enabling both the window and scatter gather.
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//
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WRITE_EPIC_REGISTER( WindowRegisters->TranslatedBaseRegister,
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*(PULONG)&TBase );
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WRITE_EPIC_REGISTER( WindowRegisters->WindowMaskRegister,
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*(PULONG)&PciMask );
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WRITE_EPIC_REGISTER( WindowRegisters->WindowBaseRegister,
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*(PULONG)&PciBase );
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//
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// Invalidate any translations that might have existed for this window.
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//
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WRITE_EPIC_REGISTER( WindowRegisters->WindowTbiaRegister, 0 );
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//
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// Enable the translation buffer inside of the EPIC.
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//
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RtlZeroMemory( &Ecsr, sizeof(EPIC_ECSR) );
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Ecsr.Tenb = 1;
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//
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// Tri state parity checking - keep disabled if not determined
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// yet. otherwise, Whack the PCI parity disable bit with the stored
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// value
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//
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if (HalDisablePCIParityChecking == 0xffffffff) {
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Ecsr.Dpec = 1;
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} else {
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Ecsr.Dpec = HalDisablePCIParityChecking;
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}
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#if HALDBG
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if (HalDisablePCIParityChecking == 0) {
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DbgPrint("apecs: PCI Parity Checking ON\n");
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} else if (HalDisablePCIParityChecking == 1) {
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DbgPrint("apecs: PCI Parity Checking OFF\n");
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} else {
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DbgPrint("apecs: PCI Parity Checking OFF - not set by ARC yet\n");
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}
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#endif
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RegisterQva =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister;
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WRITE_EPIC_REGISTER( RegisterQva,
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*(PULONG)&Ecsr );
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#if DBG
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//
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// Dump the EPIC registers.
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//
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DumpEpic();
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#endif //DBG
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return;
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}
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ULONG
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READ_EPIC_REGISTER(
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PVOID
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);
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#if DBG
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VOID
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DumpEpic(
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VOID
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)
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/*++
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Routine Description:
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Read the interesting EPIC registers and print them to the debug port.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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PVOID RegisterQva;
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ULONG Value;
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DbgPrint( "Dumping the EPIC registers\n" );
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RegisterQva =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->EpicControlAndStatusRegister;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "ECSR = %x\n", Value );
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RegisterQva =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TranslatedBase1Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "TBASE1 = %x\n", Value );
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RegisterQva =
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&((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->TranslatedBase2Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "TBASE2 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciBase1Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "PCIBASE1 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciBase2Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "PCIBASE2 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciMask1Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "PCIMASK1 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->PciMask2Register;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "PCIMASK2 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr0;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "HAXR0 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr1;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "HAXR1 = %x\n", Value );
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RegisterQva = &((PEPIC_CSRS)(APECS_EPIC_BASE_QVA))->Haxr2;
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Value = READ_EPIC_REGISTER( RegisterQva );
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DbgPrint( "HAXR2 = %x\n", Value );
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DbgPrint( "--end EPIC dump\n\n" );
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return;
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}
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#endif //DBG
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