648 lines
15 KiB
C
648 lines
15 KiB
C
/*++
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Copyright (c) 1993, 1996 Digital Equipment Corporation
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Module Name:
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apecs.h
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Abstract:
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This file defines the structures and definitions common to all
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APECS-based platforms.
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Author:
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Joe Notarangelo 12-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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Chao Chen 31-Aug-1995 Fix the broken Comanche register data structure.
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Gene Morgan 27-Feb-1996 Add missing Comanche register defns
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--*/
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#ifndef _APECSH_
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#define _APECSH_
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//
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// Define QVA constants for APECS.
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//
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#if !defined(QVA_ENABLE)
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#define QVA_ENABLE (0xA0000000) // Identify VA as a QVA
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#endif //!QVA_ENABLE
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#define QVA_SELECTORS (0xE0000000) // QVA identification mask
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#define IO_BIT_SHIFT 0x05 // Bits to shift QVA
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#define IO_BYTE_OFFSET 0x20 // Offset to next byte
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#define IO_SHORT_OFFSET 0x40 // Offset to next short
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#define IO_LONG_OFFSET 0x80 // Offset to next long
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#define IO_BYTE_LEN 0x00 // Byte length
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#define IO_WORD_LEN 0x08 // Word length
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#define IO_TRIBYTE_LEN 0x10 // TriByte length
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#define IO_LONG_LEN 0x18 // Longword length
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//
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// Define size of I/O and memory space for APECS
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//
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#define PCI_MAX_IO_ADDRESS 0xFFFFFF // 16 Mb of IO Space
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#define PCI_MAX_SPARSE_MEMORY_ADDRESS ((128*1024*1024) - 1)
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#define PCI_MIN_DENSE_MEMORY_ADDRESS PCI_MAX_SPARSE_MEMORY_ADDRESS + 1
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#define PCI_MAX_DENSE_MEMORY_ADDRESS (0xa0000000 -1) // 2.5 Gb
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//
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// Constant used by dense space I/O routines
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//
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#define PCI_DENSE_BASE_PHYSICAL_SUPERPAGE 0xfffffc0300000000
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#if !defined(_LANGUAGE_ASSEMBLY)
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//
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// QVA
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// HAL_MAKE_QVA(
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// ULONGLONG PhysicalAddress
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// )
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//
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// Routine Description:
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//
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// This macro returns the Qva for a physical address in system space.
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//
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// Arguments:
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//
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// PhysicalAddress - Supplies a 64-bit physical address.
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//
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// Return Value:
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//
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// The Qva associated with the physical address.
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//
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#define HAL_MAKE_QVA(PA) \
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( (PVOID)( QVA_ENABLE | (ULONG)((PA) >> IO_BIT_SHIFT) ) )
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//
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// Define physical address spaces for APECS.
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//
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#define APECS_COMANCHE_BASE_PHYSICAL ((ULONGLONG)0x180000000)
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#define APECS_EPIC_BASE_PHYSICAL ((ULONGLONG)0x1A0000000)
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#define APECS_PCI_INTACK_BASE_PHYSICAL ((ULONGLONG)0x1B0000000)
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#define APECS_PCI_IO_BASE_PHYSICAL ((ULONGLONG)0x1C0000000)
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#define APECS_PCI_CONFIG_BASE_PHYSICAL ((ULONGLONG)0x1E0000000)
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#define APECS_PCI_MEMORY_BASE_PHYSICAL ((ULONGLONG)0x200000000)
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#define APECS_PCI_DENSE_BASE_PHYSICAL ((ULONGLONG)0x300000000)
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#define APECS_PCI_CONFIG_BASE_QVA (HAL_MAKE_QVA(APECS_PCI_CONFIG_BASE_PHYSICAL))
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#define EPIC_HAXR1_BASE_PHYSICAL ((ULONGLONG)0x1A00001A0)
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#define EPIC_HAXR2_BASE_PHYSICAL ((ULONGLONG)0x1A00001C0)
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#define EPIC_HAXR1_QVA (HAL_MAKE_QVA(EPIC_HAXR1_BASE_PHYSICAL))
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#define EPIC_HAXR2_QVA (HAL_MAKE_QVA(EPIC_HAXR2_BASE_PHYSICAL))
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//
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// Define COMANCHE CSRs.
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//
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#define APECS_COMANCHE_BASE_QVA (HAL_MAKE_QVA(APECS_COMANCHE_BASE_PHYSICAL))
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//
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// N.B. The structure below defines the address offsets of the control
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// registers when used with the base QVA. It does NOT define the
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// size or structure of the individual registers.
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//
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typedef struct _COMANCHE_CSRS{
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UCHAR GeneralControlRegister;
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UCHAR Reserved;
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UCHAR ErrorAndDiagnosticStatusRegister;
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UCHAR TagEnableRegister;
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UCHAR ErrorLowAddressRegister;
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UCHAR ErrorHighAddressRegister;
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UCHAR Ldx_lLowAddressRegister;
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UCHAR Ldx_lHighAddressRegister;
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UCHAR Reserved1[8];
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UCHAR GlobalTimingRegister;
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UCHAR RefreshTimingRegister;
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UCHAR VideoFramePointerRegister;
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UCHAR PresenceDetectLowDataRegister;
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UCHAR PresenceDetectHighDataRegister;
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UCHAR Reserved2[43];
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UCHAR Bank0BaseAddressRegister;
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UCHAR Bank1BaseAddressRegister;
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UCHAR Bank2BaseAddressRegister;
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UCHAR Bank3BaseAddressRegister;
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UCHAR Bank4BaseAddressRegister;
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UCHAR Bank5BaseAddressRegister;
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UCHAR Bank6BaseAddressRegister;
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UCHAR Bank7BaseAddressRegister;
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UCHAR Bank8BaseAddressRegister;
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UCHAR Reserved3[7];
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UCHAR Bank0ConfigurationRegister;
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UCHAR Bank1ConfigurationRegister;
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UCHAR Bank2ConfigurationRegister;
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UCHAR Bank3ConfigurationRegister;
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UCHAR Bank4ConfigurationRegister;
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UCHAR Bank5ConfigurationRegister;
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UCHAR Bank6ConfigurationRegister;
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UCHAR Bank7ConfigurationRegister;
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UCHAR Bank8ConfigurationRegister;
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UCHAR Reserved4[7];
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UCHAR Bank0TimingRegisterA;
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UCHAR Bank1TimingRegisterA;
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UCHAR Bank2TimingRegisterA;
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UCHAR Bank3TimingRegisterA;
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UCHAR Bank4TimingRegisterA;
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UCHAR Bank5TimingRegisterA;
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UCHAR Bank6TimingRegisterA;
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UCHAR Bank7TimingRegisterA;
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UCHAR Bank8TimingRegisterA;
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UCHAR Reserved5[7];
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UCHAR Bank0TimingRegisterB;
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UCHAR Bank1TimingRegisterB;
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UCHAR Bank2TimingRegisterB;
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UCHAR Bank3TimingRegisterB;
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UCHAR Bank4TimingRegisterB;
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UCHAR Bank5TimingRegisterB;
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UCHAR Bank6TimingRegisterB;
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UCHAR Bank7TimingRegisterB;
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UCHAR Bank8TimingRegisterB;
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} COMANCHE_CSRS, *PCOMANCHE_CSRS;
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//
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// Define formats of useful COMANCHE registers.
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//
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//
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// Error Diagnostic and Status Register
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//
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typedef union _COMANCHE_EDSR{
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struct{
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ULONG Losterr: 1;
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ULONG Bctaperr: 1;
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ULONG Bctcperr: 1;
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ULONG Nxmerr: 1;
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ULONG Dmacause: 1;
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ULONG Viccause: 1;
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ULONG Creqcause: 3;
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ULONG Reserved: 4;
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ULONG Pass2: 1;
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ULONG Ldxllock: 1;
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ULONG Wrpend: 1;
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};
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ULONG all;
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} COMANCHE_EDSR, *PCOMANCHE_EDSR;
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//
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// General Control Register
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//
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typedef union _COMANCHE_GCR {
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struct {
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ULONG Reserved1: 1;
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ULONG Sysarb: 2;
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ULONG Reserved2: 1;
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ULONG Widemem: 1;
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ULONG Bcen: 1;
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ULONG Bcnoalloc: 1;
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ULONG Bclongwr: 1;
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ULONG Bcigntflag: 1;
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ULONG Bcfrctflag: 1;
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ULONG Bcfrcd: 1;
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ULONG Bcfrcz: 1;
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ULONG Bcfrcp: 1;
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ULONG Bcbadap: 1;
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ULONG Reserved3: 2;
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};
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ULONG all;
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} COMANCHE_GCR, *PCOMANCHE_GCR;
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//
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// Tag Enable Register
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//
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typedef union _COMANCHE_TER {
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struct {
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ULONG Tagen: 16; // Bit zero is reserved and MBZ
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};
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ULONG all;
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} COMANCHE_TER, *PCOMANCHE_TER;
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//
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// Bank<n> Base Address Register [0..8]
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//
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typedef union _COMANCHE_BASE_ADDRESS_REGISTER {
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struct {
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ULONG Reserved: 5;
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ULONG BaseAdr: 11;
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};
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ULONG all;
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} COMANCHE_BASE_ADDRESS_REGISTER, *PCOMANCHE_BASE_ADDRESS_REGISTER;
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//
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// Bank<n> Configuration Register [0..8]
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//
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typedef union _COMANCHE_BANK_CONFIGURATION_REGISTER {
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struct {
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ULONG SetValid: 1;
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ULONG SetSize: 4;
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ULONG SetSubEna: 1;
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ULONG SetColSel: 3;
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ULONG Reserved: 7;
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};
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ULONG all;
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}COMANCHE_BANK_CONFIGURATION_REGISTER, *PCOMANCHE_BANK_CONFIGURATION_REGISTER;
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//
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// Define EPIC CSRs.
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//
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#define APECS_EPIC_BASE_QVA (HAL_MAKE_QVA(APECS_EPIC_BASE_PHYSICAL))
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//
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// N.B. The structure below defines the address offsets of the control
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// registers when used with the base QVA. It does NOT define the
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// size or structure of the individual registers.
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//
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typedef struct _EPIC_CSRS{
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UCHAR EpicControlAndStatusRegister;
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UCHAR SysbusErrorAddressRegister;
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UCHAR PciErrorAddressRegister;
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UCHAR DummyRegister1;
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UCHAR DummyRegister2;
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UCHAR DummyRegister3;
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UCHAR TranslatedBase1Register;
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UCHAR TranslatedBase2Register;
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UCHAR PciBase1Register;
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UCHAR PciBase2Register;
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UCHAR PciMask1Register;
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UCHAR PciMask2Register;
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UCHAR Haxr0;
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UCHAR Haxr1;
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UCHAR Haxr2;
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UCHAR DummyRegister4;
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UCHAR TlbTag0Register;
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UCHAR TlbTag1Register;
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UCHAR TlbTag2Register;
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UCHAR TlbTag3Register;
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UCHAR TlbTag4Register;
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UCHAR TlbTag5Register;
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UCHAR TlbTag6Register;
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UCHAR TlbTag7Register;
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UCHAR TlbData0Register;
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UCHAR TlbData1Register;
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UCHAR TlbData2Register;
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UCHAR TlbData3Register;
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UCHAR TlbData4Register;
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UCHAR TlbData5Register;
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UCHAR TlbData6Register;
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UCHAR TlbData7Register;
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UCHAR TbiaRegister;
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} EPIC_CSRS, *PEPIC_CSRS;
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//
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// Define formats of useful EPIC registers. Note that P1 is a vestige,
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// and direct access for P2 definitions are the default.
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//
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typedef union _EPIC_ECSR{
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struct{
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ULONG Tenb: 1;
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ULONG Prst: 1;
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ULONG Penb: 1;
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ULONG Dcei: 1;
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ULONG Rsvd1: 1;
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ULONG Iort: 1;
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ULONG Lost: 1;
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ULONG Rdwr: 1;
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ULONG Ddpe: 1;
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ULONG Iope: 1;
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ULONG Tabt: 1;
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ULONG Ndev: 1;
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ULONG Cmrd: 1;
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ULONG Umrd: 1;
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ULONG Iptl: 1;
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ULONG Merr: 1;
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ULONG DisRdByp: 2;
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ULONG Rsvd2: 14;
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} P1;
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struct{
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ULONG Tenb: 1;
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ULONG Rsvd1: 1;
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ULONG Penb: 1;
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ULONG Dcei: 1;
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ULONG Dpec: 1;
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ULONG Iort: 1;
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ULONG Lost: 1;
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ULONG Rsvd2: 1;
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ULONG Ddpe: 1;
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ULONG Iope: 1;
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ULONG Tabt: 1;
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ULONG Ndev: 1;
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ULONG Cmrd: 1;
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ULONG Umrd: 1;
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ULONG Iptl: 1;
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ULONG Merr: 1;
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ULONG DisRdByp: 2;
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ULONG Pcmd: 4;
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ULONG Rsvd3: 9;
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ULONG Pass2: 1;
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};
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ULONG all;
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} EPIC_ECSR, *PEPIC_ECSR;
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typedef struct _EPIC_PCIMASK{
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ULONG Reserved: 20;
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ULONG MaskValue: 12;
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} EPIC_PCIMASK, *PEPIC_PCIMASK;
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typedef struct _EPIC_PCIBASE{
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ULONG Reserved: 18;
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ULONG Sgen: 1;
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ULONG Wenr: 1;
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ULONG BaseValue: 12;
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} EPIC_PCIBASE, *PEPIC_PCIBASE;
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typedef struct _EPIC_TBASE{
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ULONG Reserved: 9;
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ULONG TBase: 23;
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} EPIC_TBASE, *PEPIC_TBASE;
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//
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// DMA Window Values.
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//
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// The APECs will be initialized to allow 2 DMA windows.
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// The first window will be for the use of of ISA devices and DMA slaves
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// and therefore must have logical addresses below 16MB.
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// The second window will be for bus masters (non-ISA) and so may be
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// above 16MB.
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//
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// The arrangement of the windows will be as follows:
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//
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// Window Logical Start Address Window Size
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// ------ --------------------- -----------
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// Isa 8MB 8MB
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// Master 16MB 16MB
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//
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#define ISA_DMA_WINDOW_BASE (__8MB)
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#define ISA_DMA_WINDOW_SIZE (__8MB)
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#define MASTER_DMA_WINDOW_BASE (__16MB)
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#define MASTER_DMA_WINDOW_SIZE (__16MB)
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//
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// Define the software control registers for a DMA window.
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//
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typedef struct _WINDOW_CONTROL_REGISTERS{
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PVOID WindowBase;
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ULONG WindowSize;
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PVOID TranslatedBaseRegister;
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PVOID WindowBaseRegister;
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PVOID WindowMaskRegister;
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PVOID WindowTbiaRegister;
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} WINDOW_CONTROL_REGISTERS, *PWINDOW_CONTROL_REGISTERS;
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//
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// Define types of windows.
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//
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typedef enum _APECS_WINDOW_NUMBER{
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ApecsIsaWindow,
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ApecsMasterWindow
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} APECS_WINDOW_NUMBER, *PAPECS_WINDOW_NUMBER;
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//
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// Define APECS Window Control routines.
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//
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VOID
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HalpApecsInitializeSfwWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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APECS_WINDOW_NUMBER WindowNumber
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);
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VOID
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HalpApecsProgramDmaWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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PVOID MapRegisterBase
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);
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//
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// VOID
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// INITIALIZE_ISA_DMA_CONTROL(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Initialize the DMA Control software window registers for the ISA
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_ISA_DMA_CONTROL( WR ) \
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HalpApecsInitializeSfwWindow( (WR), ApecsIsaWindow );
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//
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// VOID
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// INITIALIZE_MASTER_DMA_CONTROL(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Initialize the DMA Control software window registers for the ISA
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_MASTER_DMA_CONTROL( WR ) \
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HalpApecsInitializeSfwWindow( (WR), ApecsMasterWindow );
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//
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// VOID
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// INITIALIZE_DMA_WINDOW(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters,
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// PTRANSLATION_ENTRY MapRegisterBase
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// )
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//
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// Routine Description:
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//
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// Program the control windows so that DMA can be started to the
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window register
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// control structure.
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//
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// MapRegisterBase - Supplies the logical address of the scatter/gather
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// array in system memory.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_DMA_WINDOW( WR, MRB ) \
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HalpApecsProgramDmaWindow( (WR), (MRB) );
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//
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// VOID
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// INVALIDATE_DMA_TRANSLATIONS(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Invalidate all of the cached translations for a DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control
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// registers.
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//
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// Return Value:
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//
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// None.
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//
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#define INVALIDATE_DMA_TRANSLATIONS( WR ) \
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WRITE_EPIC_REGISTER( \
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((PWINDOW_CONTROL_REGISTERS)WR)->WindowTbiaRegister, 0 );
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//
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// Define the format of a translation entry aka a scatter/gather entry
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// or map register.
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//
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typedef struct _TRANSLATION_ENTRY{
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ULONG Valid: 1;
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ULONG Pfn: 31;
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ULONG Reserved;
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} TRANSLATION_ENTRY, *PTRANSLATION_ENTRY;
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||
//
|
||
// VOID
|
||
// HAL_MAKE_VALID_TRANSLATION(
|
||
// PTRANSLATION_ENTRY Entry,
|
||
// ULONG PageFrameNumber
|
||
// )
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// Make the scatter/gather entry pointed to by Entry valid with
|
||
// a translation to the page indicated by PageFrameNumber.
|
||
//
|
||
// Arguments:
|
||
//
|
||
// Entry - Supplies a pointer to the translation entry to make valid.
|
||
//
|
||
// PageFrameNumber - Supplies the page frame of the valid translation.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
|
||
#define HAL_MAKE_VALID_TRANSLATION( ENTRY, PFN ) \
|
||
{ \
|
||
(ENTRY)->Valid = 1; \
|
||
(ENTRY)->Pfn = PFN; \
|
||
(ENTRY)->Reserved = 0; \
|
||
}
|
||
|
||
|
||
//
|
||
// VOID
|
||
// HAL_INVALIDATE_TRANSLATION(
|
||
// PTRANSLATION_ENTRY Entry
|
||
// )
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// Invalidate the translation indicated by Entry.
|
||
//
|
||
// Arguments:
|
||
//
|
||
// Entry - Supplies a pointer to the translation to be invalidated.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
|
||
#define HAL_INVALIDATE_TRANSLATION( ENTRY ) \
|
||
(ENTRY)->Valid = 0;
|
||
|
||
//
|
||
// APECS-specific functions.
|
||
//
|
||
|
||
VOID
|
||
WRITE_COMANCHE_REGISTER(
|
||
IN PVOID RegisterQva,
|
||
IN ULONG Value
|
||
);
|
||
|
||
ULONG
|
||
READ_COMANCHE_REGISTER(
|
||
IN PVOID RegisterQva
|
||
);
|
||
|
||
VOID
|
||
WRITE_EPIC_REGISTER(
|
||
IN PVOID RegisterQva,
|
||
IN ULONG Value
|
||
);
|
||
|
||
ULONG
|
||
READ_EPIC_REGISTER(
|
||
IN PVOID RegisterQva
|
||
);
|
||
|
||
#endif //!_LANGUAGE_ASSEMBLY
|
||
|
||
#endif //_APECSH_
|