568 lines
15 KiB
C
568 lines
15 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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ciaaddr.c
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Abstract:
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This module contains the platform dependent code to create bus addreses
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and QVAs for the Alcor system.
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Author:
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Joe Notarangelo 30-Jun-1994
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Steve Brooks 30-Jun-1994
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "eisa.h"
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typedef PVOID QUASI_VIRTUAL_ADDRESS;
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QUASI_VIRTUAL_ADDRESS
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HalCreateQva(
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IN PHYSICAL_ADDRESS PA,
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IN PVOID VA
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);
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BOOLEAN
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HalpTranslateSystemBusAddress(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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)
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/*++
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Routine Description:
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This function returns the system physical address for a specified I/O bus
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address. The return value is suitable for use in a subsequent call to
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MmMapIoSpace.
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Arguments:
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BusHandler - Registered BUSHANDLER for the target configuration space
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Supplies the bus handler (bus no, interface type).
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RootHandler - Registered BUSHANDLER for the orginating
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HalTranslateBusAddress request.
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BusAddress - Supplies the bus relative address.
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AddressSpace - Supplies the address space number for the device: 0 for
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memory and 1 for I/O space. If the desired access mode is user mode,
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then bit 1 must be TRUE.
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TranslatedAddress - Supplies a pointer to return the translated address
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Notes:
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This is a variation of what began in the MIPS code. The intel code often
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assumes that if an address is in I/O space, the bottom 32 bits of the
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physical address can be used "like" a virtual address, and are returned
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to the user. This doesn't work on MIPs machines where physical
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addresses can be larger than 32 bits.
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Since we are using superpage addresses for I/O on Alpha, we can do
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almost what is done on intel. If AddressSpace is equal to 0 or 1, then
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we assume the user is doing kernel I/O and we call HalCreateQva to
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build a Quasi Virtual Address and return that to the caller. We then
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set AddressSpace to a 1, so that the caller will not call MmMapIoSpace.
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The Caller will use the low 32 bits of the physical address we return
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as the VA. (Which we built a QVA in).
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If the caller wants to access EISA I/O or Memory through user mode, then
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the caller must set bit 1 in AddressSpace to a 1 (AddressSpace=2 or 3,
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depending on whether EISA I/O or Memory), then the caller is returned the
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34 bit Physical address. The caller will then call MmMapIoSpace, or
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ZwMapViewOfSection which in turn calls HalCreateQva to build a QVA out
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of a VA mapped through the page tables.
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**** Note ****
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The QVA in user mode can only be used via the user-mode access macros.
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Return Value:
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A return value of TRUE indicates that a system physical address
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corresponding to the supplied bus relative address and bus address
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number has been returned in TranslatedAddress.
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A return value of FALSE occurs if the translation for the address was
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not possible
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--*/
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{
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INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType;
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ULONG BusNumber = BusHandler->BusNumber;
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PVOID va = 0; // note, this is used for a placeholder
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//
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// The buses available on Alcor are EISA and PCI.
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// We support any translations for ISA devices as well,
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// since they can plug into EISA slots just fine.
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//
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if (InterfaceType != Isa &&
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InterfaceType != Eisa &&
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InterfaceType != PCIBus) {
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//
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// Not on this system; return nothing.
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//
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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//
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// Determine the address based on whether the bus address is in I/O space
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// or bus memory space.
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//
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switch ( (ADDRESS_SPACE_TYPE)(*AddressSpace) ) {
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case BusMemory:
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//
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// The address is in PCI memory space, kernel mode.
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//
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switch( InterfaceType ) {
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case Isa:
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//
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// Can't go above 16MB (24 Bits) for Isa Buses
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//
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if( BusAddress.LowPart >= __16MB ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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break;
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case PCIBus: {
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if ( BusAddress.LowPart > PCI_MAX_DENSE_MEMORY_ADDRESS ) {
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//
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// Unsupported dense PCI bus address.
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//
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#if HALDBG
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DbgPrint ("Unsupported PCI address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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else if( BusAddress.LowPart >= PCI_MIN_DENSE_MEMORY_ADDRESS &&
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BusAddress.LowPart <= PCI_MAX_DENSE_MEMORY_ADDRESS ) {
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#if HALDBG
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DbgPrint ("Translating PCI kernel dense address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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//
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// Bus Address is in dense PCI memory space
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//
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//
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// QVA, as such, is simply the PCI bus address
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//
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TranslatedAddress->LowPart = BusAddress.LowPart;
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//
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// clear high longword for QVA
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//
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TranslatedAddress->HighPart = 0;
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//
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// dont let the user call MmMapIoSpace
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//
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*AddressSpace = 1;
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return (TRUE);
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}
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//
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// Bus Address is in sparse PCI memory space
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//
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#if HALDBG
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DbgPrint ("Translating PCI kernel sparse address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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break;
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} // case PCIBus
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case Eisa:
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break;
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} // switch( InterfaceType )
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = CIA_PCI_SPARSE_MEMORY_PHYSICAL;
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TranslatedAddress->QuadPart +=
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((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT);
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//
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// Now call HalCreateQva. This will create a QVA
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// that we'll return to the caller. Then we will implicitly set
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// AddressSpace to a 1. The caller then will not call MmMapIoSpace
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// and will use the address we return as a VA.
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//
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TranslatedAddress->LowPart = (ULONG)HalCreateQva(
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*TranslatedAddress,
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va);
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TranslatedAddress->HighPart = 0; // clear high longword for QVA
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*AddressSpace = 1; // don't let the user call
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// MmMapIoSpace
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return(TRUE);
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case BusIo:
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//
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// The address is in PCI I/O space, kernel mode.
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//
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switch( InterfaceType ) {
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case Isa:
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//
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// Can't go above 64KB (16 Bits) for Isa Buses
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//
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if( BusAddress.LowPart >= __64K ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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break;
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case PCIBus:
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//
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// PCI IO space is always below 64MB (26 Bits) BusAddress
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// If the address cannot be mapped, just return FALSE.
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//
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if( BusAddress.LowPart >= __64MB ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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break;
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case Eisa:
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break;
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} // switch( InterfaceType )
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = CIA_PCI_SPARSE_IO_PHYSICAL;
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TranslatedAddress->QuadPart +=
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((ULONGLONG)BusAddress.LowPart << IO_BIT_SHIFT);
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//
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// Now call HalCreateQva. This will create a QVA
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// that we'll return to the caller. Then we will implicitly set
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// AddressSpace to a 1. The caller then will not call MmMapIoSpace
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// and will use the address we return as a VA.
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TranslatedAddress->LowPart = (ULONG)HalCreateQva(
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*TranslatedAddress,
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va);
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TranslatedAddress->HighPart = 0; // clear high longword for QVA
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*AddressSpace = 1; // make sure user doesn't call
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// MmMapIoSpace.
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return(TRUE);
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case UserBusMemory:
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//
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// The address is in PCI memory space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = CIA_PCI_SPARSE_MEMORY_PHYSICAL;
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += (BusAddress.LowPart << IO_BIT_SHIFT);
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*AddressSpace = 0; // Let the user call MmMapIoSpace
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return(TRUE);
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case UserBusIo:
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//
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// The address is in PCI I/O space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = CIA_PCI_SPARSE_IO_PHYSICAL;
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += (BusAddress.LowPart << IO_BIT_SHIFT);
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*AddressSpace = 0; // Let the user call MmMapIoSpace
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return(TRUE);
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case KernelPciDenseMemory:
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case UserPciDenseMemory:
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//
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// The address is in PCI memory space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = CIA_PCI_DENSE_MEMORY_PHYSICAL;
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += BusAddress.LowPart;
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*AddressSpace = 0; // Let the user call MmMapIoSpace
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return(TRUE);
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default:
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//
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// Unsupported address space.
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//
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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}
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PVOID
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HalCreateQva(
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IN PHYSICAL_ADDRESS PA,
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IN PVOID VA
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)
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/*++
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Routine Description:
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This function is called two ways. First, from HalTranslateBusAddress,
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if the caller is going to run in kernel mode and use superpages.
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The second way is if the user is going to access in user mode.
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MmMapIoSpace or ZwViewMapOfSection will call this.
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If the input parameter VA is zero, then we assume super page and build
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a QUASI virtual address that is only usable by calling the hal I/O
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access routines.
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if the input parameter VA is non-zero, we assume the user has either
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called MmMapIoSpace or ZwMapViewOfSection and will use the user mode
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access macros.
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If the PA is not a sparse I/O space address (PCI I/O, PCI Memory),
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then return the VA as the QVA.
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Arguments:
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PA - the physical address generated by HalTranslateBusAddress
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VA - the virtual address returned by MmMapIoSpace
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Return Value:
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The returned value is a quasi virtual address in that it can be
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added to and subtracted from, but it cannot be used to access the
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bus directly. The top bits are set so that we can trap invalid
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accesses in the memory management subsystem. All access should be
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done through the Hal Access Routines in *ioacc.s if it was a superpage
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kernel mode access. If it is usermode, then the user mode access
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macros must be used.
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--*/
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{
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PHYSICAL_ADDRESS PhysicalOffset;
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PVOID qva;
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if( (PA.QuadPart >= CIA_PCI_DENSE_MEMORY_PHYSICAL) &&
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(PA.QuadPart <= (CIA_PCI_DENSE_MEMORY_PHYSICAL +
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PCI_MAX_DENSE_MEMORY_ADDRESS)) ){
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//
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// Kernel-mode physical dense address, return VA.
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//
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return(VA);
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} else if( (PA.QuadPart >=
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(CIA_PCI_DENSE_MEMORY_PHYSICAL | EV5_USER_IO_ADDRESS_SPACE) ) &&
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(PA.QuadPart <
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(CIA_PCI_DENSE_MEMORY_PHYSICAL | EV5_USER_IO_ADDRESS_SPACE +
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PCI_MAX_DENSE_MEMORY_ADDRESS) ) ){
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//
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// User-mode physical dense address, return VA.
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//
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return(VA);
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} else {
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//
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// The physical address is within one of the sparse I/O spaces.
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//
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if (VA == 0) {
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PhysicalOffset.QuadPart = PA.QuadPart - CIA_QVA_PHYSICAL_BASE;
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qva = (PVOID)(PhysicalOffset.QuadPart >> IO_BIT_SHIFT);
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} else {
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qva = (PVOID)((ULONG)VA >> IO_BIT_SHIFT);
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}
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qva = (PVOID)((ULONG)qva | QVA_ENABLE);
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return(qva);
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}
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}
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PVOID
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HalDereferenceQva(
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PVOID Qva,
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INTERFACE_TYPE InterfaceType,
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ULONG BusNumber
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)
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/*++
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Routine Description:
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This function performs the inverse of the HalCreateQva for I/O addresses
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that are memory-mapped (i.e. the quasi-virtual address was created from
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a virtual address rather than a physical address).
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Arguments:
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Qva - Supplies the quasi-virtual address to be converted back to a
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virtual address.
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InterfaceType - Supplies the interface type of the bus to which the
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Qva pertains.
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BusNumber - Supplies the bus number of the bus to which the Qva pertains.
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Return Value:
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The Virtual Address from which the quasi-address was originally created
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is returned.
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--*/
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{
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//
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// For Alcor we support three bus types:
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//
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// Isa
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// Eisa
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// PCIBus
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//
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switch (InterfaceType ){
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case Isa:
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case Eisa:
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case PCIBus:
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//
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// Support PCI Dense space: check to see if it's really
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// a QVA.
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//
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if ( ((ULONG) Qva & QVA_SELECTORS) == QVA_ENABLE ) {
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return( (PVOID)( (ULONG)Qva << IO_BIT_SHIFT ) );
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} else {
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return (Qva);
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}
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break;
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default:
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return NULL;
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}
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}
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