775 lines
22 KiB
C
775 lines
22 KiB
C
/*++
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Copyright (c) 1995 Digital Equipment Corporation
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Module Name:
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errplat.h
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Abstract:
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Definitions for the platform specific correctable and uncorrectable error
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frames for processors and systems.
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Author:
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Joe Notarangelo 10-Mar-1995
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Chao Chen 24-Apr-1995
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Environment:
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Kernel mode only.
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Revision History:
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0.1 28-Feb-1995 Joe Notarangelo Initial version.
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0.2 10-Mar-1995 Joe Notarangelo Incorporate initial review comments from
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6-Mar-95 review with: C. Chen, S. Jenness,
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Bala, E. Rehm.
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0.3 24-Apr-1995 Chao Chen Made into .h file for inclusion by other
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modules.
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0.4 Jun-July-1995 Bala Nagarajan Added Uncorrectable Error frames for
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APECS, SABLE, GAMMA etc.
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--*/
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#ifndef ERRPLAT_H
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#define ERRPLAT_H
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/*
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*
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* Processor specific definitions for error frame.
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*
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*/
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//
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// EV5:
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//
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//
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// Processor information structure for processor detected correctable read
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// on the EV5.
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//
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typedef struct PROCESSOR_EV5_CORRECTABLE{
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ULONGLONG EiAddr;
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ULONGLONG FillSyn;
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ULONGLONG EiStat;
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ULONGLONG BcConfig;
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ULONGLONG BcControl;
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} PROCESSOR_EV5_CORRECTABLE, *PPROCESSOR_EV5_CORRECTABLE;
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//
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// Processor information structure for processor-detected uncorrectable errors
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// on the EV5.
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//
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typedef struct PROCESSOR_EV5_UNCORRECTABLE{
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ULONGLONG IcPerrStat;
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ULONGLONG DcPerrStat;
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ULONGLONG ScStat;
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ULONGLONG ScAddr;
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ULONGLONG EiStat;
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ULONGLONG BcTagAddr;
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ULONGLONG EiAddr;
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ULONGLONG FillSyn;
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ULONGLONG BcConfig;
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ULONGLONG BcControl;
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} PROCESSOR_EV5_UNCORRECTABLE, *PPROCESSOR_EV5_UNCORRECTABLE;
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//
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// EV4(5):
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//
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//
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// Processor information structure for processor detected correctable read
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// on the EV4(5).
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//
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typedef struct PROCESSOR_EV4_CORRECTABLE{
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ULONGLONG BiuStat;
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ULONGLONG BiuAddr;
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ULONGLONG AboxCtl;
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ULONGLONG BiuCtl;
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ULONGLONG CStat; // a.k.a. DcStat for EV4
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} PROCESSOR_EV4_CORRECTABLE, *PPROCESSOR_EV4_CORRECTABLE;
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//
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// Processor information structure for processor detected uncorrectable errors
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// on the EV4(5).
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//
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typedef struct PROCESSOR_EV4_UNCORRECTABLE{
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ULONGLONG BiuStat;
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ULONGLONG BiuAddr;
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ULONGLONG AboxCtl;
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ULONGLONG BiuCtl;
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ULONGLONG CStat; // a.k.a. DcStat for EV4
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ULONGLONG BcTag;
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ULONGLONG FillAddr;
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ULONGLONG FillSyndrome;
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} PROCESSOR_EV4_UNCORRECTABLE, *PPROCESSOR_EV4_UNCORRECTABLE;
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//
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// LCA:
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//
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//
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// Processor information structure for processor detected correctable read
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// on the LCA.
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//
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typedef struct PROCESSOR_LCA_CORRECTABLE{
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ULONG VersionNumber; // Version Number of this structure not the LCA.
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ULONGLONG Esr;
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ULONGLONG Ear;
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ULONGLONG AboxCtl;
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ULONG BankConfig0;
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ULONG BankConfig1;
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ULONG BankConfig2;
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ULONG BankConfig3;
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ULONG BankMask0;
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ULONG BankMask1;
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ULONG BankMask2;
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ULONG BankMask3;
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ULONG Car;
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ULONG Gtr;
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} PROCESSOR_LCA_CORRECTABLE, *PPROCESSOR_LCA_CORRECTABLE;
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//
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// Processor information structure for processor detected uncorrectable errors
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// on the LCA.
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//
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typedef struct PROCESSOR_LCA_UNCORRECTABLE{
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ULONG VersionNumber; // Version Number of this structure not the LCA.
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ULONGLONG CStat; // a.k.a. DcStat for LCA4
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ULONGLONG Esr;
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ULONGLONG Ear;
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ULONGLONG IocStat0;
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ULONGLONG IocStat1;
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ULONGLONG AboxCtl;
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ULONGLONG MmCsr;
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ULONGLONG BankConfig0;
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ULONGLONG BankConfig1;
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ULONGLONG BankConfig2;
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ULONGLONG BankConfig3;
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ULONGLONG BankMask0;
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ULONGLONG BankMask1;
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ULONGLONG BankMask2;
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ULONGLONG BankMask3;
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ULONGLONG Car;
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ULONGLONG Gtr;
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} PROCESSOR_LCA_UNCORRECTABLE, *PPROCESSOR_LCA_UNCORRECTABLE;
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//
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// The generic raw processor frame.
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//
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typedef union _RAW_PROCESSOR_FRAME{
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PROCESSOR_EV5_CORRECTABLE Ev5Correctable;
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PROCESSOR_EV5_UNCORRECTABLE Ev5Uncorrectable;
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PROCESSOR_EV4_CORRECTABLE Ev4Correctable;
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PROCESSOR_EV4_UNCORRECTABLE Ev4Uncorrectable;
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PROCESSOR_LCA_CORRECTABLE LcaCorrectable;
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PROCESSOR_LCA_UNCORRECTABLE LcaUncorrectable;
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} RAW_PROCESSOR_FRAME, *PRAW_PROCESSOR_FRAME;
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/*
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*
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* System specific definitions for error frame.
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*
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*/
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//
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// Cia:
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//
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//
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// Cia configuration information
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//
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typedef struct _CIA_CONFIGURATION{
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ULONG CiaRev;
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ULONG CiaCtrl;
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ULONG Mcr;
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ULONG Mba0;
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ULONG Mba2;
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ULONG Mba4;
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ULONG Mba6;
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ULONG Mba8;
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ULONG MbaA;
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ULONG MbaC;
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ULONG MbaE;
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ULONG Tmg0;
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ULONG Tmg1;
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ULONG Tmg2;
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ULONG CacheCnfg;
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ULONG Scr;
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} CIA_CONFIGURATION, *PCIA_CONFIGURATION;
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//
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// Cia system detected correctable.
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//
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typedef struct _CIA_CORRECTABLE_FRAME{
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ULONG VersionNumber; // Version Number of this structure.
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ULONG CiaErr;
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ULONG CiaStat;
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ULONG CiaSyn;
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ULONG MemErr0;
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ULONG MemErr1;
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ULONG PciErr0;
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ULONG PciErr1;
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ULONG PciErr2;
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CIA_CONFIGURATION Configuration;
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} CIA_CORRECTABLE_FRAME, *PCIA_CORRECTABLE_FRAME;
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//
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// Note: it appears that the only correctable errors that are detected
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// are:
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//
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// a. ECC on DMA Read (memory or cache)
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// b. ECC on S/G TLB fill for DMA Read (memory or cache)
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// c. ECC on DMA Write (probably CIA)
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// d. ECC on S/G TLB fill for DMA write (memory or cache) (no PA?)
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// e. I/O Write (ASIC problem) (no PA)
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//
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//
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// Cia System-detected Uncorrectable Error
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//
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typedef struct _CIA_UNCORRECTABLE_FRAME{
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ULONG VersionNumber; // Version Number of this structure.
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ULONG CiaErr;
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ULONG ErrMask;
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ULONG CiaStat;
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ULONG CiaSyn;
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ULONG CpuErr0;
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ULONG CpuErr1;
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ULONG MemErr0;
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ULONG MemErr1;
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ULONG PciErr0;
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ULONG PciErr1;
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ULONG PciErr2;
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CIA_CONFIGURATION Configuration;
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} CIA_UNCORRECTABLE_FRAME, *PCIA_UNCORRECTABLE_FRAME;
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//
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// Apecs:
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//
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//
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// Apecs Configuration Information
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//
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typedef struct _APECS_CONFIGURATION {
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ULONG ApecsRev;
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ULONG CGcr; // General Control register
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ULONG CTer; // Tag Enable Register
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ULONG CGtr; // Global Timer Register
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ULONG CRtr; // refresh Timer register
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ULONG CBank0; // Bank Configuration registers.
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ULONG CBank1;
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ULONG CBank2;
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ULONG CBank3;
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ULONG CBank4;
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ULONG CBank5;
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ULONG CBank6;
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ULONG CBank7;
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ULONG CBank8;
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} APECS_CONFIGURATION, *PAPECS_CONFIGURATION;
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//
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// Apecs based system-detected Correctable Error
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//
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typedef struct _APECS_CORRECTABLE_FRAME{
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ULONG VersionNumber; // Version Number of this structure not the APECS.
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ULONG EpicEcsr;
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ULONG EpicSysErrAddr;
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APECS_CONFIGURATION Configuration;
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} APECS_CORRECTABLE_FRAME, *PAPECS_CORRECTABLE_FRAME;
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//
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// Note: it appears that the only correctable errors that are detected
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// are:
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//
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// a. ECC on DMA Read (memory)
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// b. ECC on S/G TLB fill for DMA Read (memory)
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//
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//
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// Apecs based system-detected Uncorrectable Error
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//
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typedef struct _APECS_UNCORRECTABLE_FRAME{
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ULONG VersionNumber; // Version Number of this structure not the APECS.
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ULONG EpicEcsr;
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ULONG ComancheEdsr;
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ULONG EpicPciErrAddr;
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ULONG EpicSysErrAddr;
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ULONG ComancheErrAddr;
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APECS_CONFIGURATION Configuration;
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} APECS_UNCORRECTABLE_FRAME, *PAPECS_UNCORRECTABLE_FRAME;
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//
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// T2, T3, T4 Chipset error frame.
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//
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typedef struct _TX_ERROR_FRAME {
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ULONGLONG Cerr1; // CBUS Error Register 1
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ULONGLONG Cerr2; // CBUS Error Register 2
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ULONGLONG Cerr3; // CBUS Error Register 3
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ULONGLONG Perr1; // PCI Error Register 1
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ULONGLONG Perr2; // PCI Error Register 2
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} TX_ERROR_FRAME, *PTX_ERROR_FRAME;
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//
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// Sable CPU Module configuration information.
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//
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typedef struct _SABLE_CPU_CONFIGURATION {
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ULONGLONG Cbctl;
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ULONGLONG Pmbx;
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ULONGLONG C4rev;
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} SABLE_CPU_CONFIGURATION, *PSABLE_CPU_CONFIGURATION;
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//
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// Sable Memory Module configuration information.
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//
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typedef struct _SABLE_MEMORY_CONFIGURATION {
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ULONGLONG Conifg; // CSR 3
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ULONGLONG EdcCtl; // Error detection/correction control register
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ULONGLONG StreamBfrCtl;
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ULONGLONG RefreshCtl;
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ULONGLONG CrdFilterCtl;
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} SABLE_MEMORY_CONFIGURATION, *PSABLE_MEMORY_CONFIGURATION;
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//
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// Sable System Configuration
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//
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typedef struct _SABLE_CONFIGURATION {
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ULONG T2Revision; // Revision number of the T2 chipset.
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ULONG NumberOfCpus; // Number of CPUs in the system.
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ULONG NumberOfMemModules; // Number of memory modules in the system.
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ULONGLONG T2IoCsr;
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SABLE_CPU_CONFIGURATION CpuConfigs[4]; // 4 is the max CPU's
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SABLE_MEMORY_CONFIGURATION MemConfigs[4]; // Maximum of 4 memory modules.
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} SABLE_CONFIGURATION, *PSABLE_CONFIGURATION;
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//
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// Sable CPU-module Error Information
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//
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typedef struct _SABLE_CPU_ERROR {
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union {
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struct {
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ULONGLONG Bcue; // BCacheUncorrectableError
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ULONGLONG Bcuea; // BCacheUncorrectableErrorAddress
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} Uncorrectable;
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struct {
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ULONGLONG Bcce; // BCacheCorrectableError
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ULONGLONG Bccea; // BCacheCorrectableErrorAddress
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} Correctable;
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};
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ULONGLONG Dter; // Duplicate Tag Error Register
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ULONGLONG Cberr; // CBUS2 Error (System Bus Error)
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ULONGLONG Cbeal; // system bus error address register low.
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ULONGLONG Cbeah; // system bus error address register high.
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} SABLE_CPU_ERROR, *PSABLE_CPU_ERROR;
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typedef struct _SABLE_MEMORY_ERROR {
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ULONGLONG MemError; // CSR0 of memory module
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ULONGLONG EdcStatus1;
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ULONGLONG EdcStatus2;
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} SABLE_MEMORY_ERROR, *PSABLE_MEMORY_ERROR;
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//
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// Sable Correctable and Uncorrectable Error Frame.
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//
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typedef struct _SABLE_ERROR_FRAME {
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SABLE_CPU_ERROR CpuError[4];
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SABLE_MEMORY_ERROR MemError[4];
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TX_ERROR_FRAME IoChipsetError;
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SABLE_CONFIGURATION Configuration;
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} SABLE_UNCORRECTABLE_FRAME, *PSABLE_UNCORRECTABLE_FRAME,
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SABLE_CORRECTABLE_FRAME, *PSABLE_CORRECTABLE_FRAME;
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//
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// Gamma CPU Module configuration information.
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//
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typedef struct _GAMMA_CPU_CONFIGURATION {
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ULONGLONG Cbctl; // Cbus2 Control Register.
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ULONGLONG Dtctr; // Duplicate Tag control register.
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ULONGLONG Creg; // Rattler Control Register.
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} GAMMA_CPU_CONFIGURATION, *PGAMMA_CPU_CONFIGURATION;
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//
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// Gamma System Configuration
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//
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typedef struct _GAMMA_CONFIGURATION {
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ULONG T2Revision; // Revision number of the T2 chipset.
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ULONG NumberOfCpus; // Number of CPUs in the system.
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ULONG NumberOfMemModules; // Number of memory modules in the system.
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ULONGLONG T2IoCsr;
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GAMMA_CPU_CONFIGURATION CpuConfigs[4]; // 4 is the max CPU's
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SABLE_MEMORY_CONFIGURATION MemConfigs[4]; // Maximum of 4 memory modules.
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} GAMMA_CONFIGURATION, *PGAMMA_CONFIGURATION;
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//
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// Gamma CPU-module Error Information
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//
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typedef struct _GAMMA_CPU_ERROR {
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ULONGLONG Esreg; // Error Summary
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union {
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struct {
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ULONGLONG Evbuer; // EVB Uncorrectable Error
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ULONGLONG Evbuear; // EVB Uncorrectable Error Address
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} Uncorrectable;
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struct {
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ULONGLONG Evbcer; // EVB Correctable Error
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ULONGLONG Evbcear; // EVB Correctable error address
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} Correctable;
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};
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ULONGLONG Vear; // Victim Error Address
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// valid only if bit 5 or bit 37
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// of Evbuer is set.
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ULONGLONG Dter; // Duplicate Tag Error Register
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ULONGLONG Cberr; // CBUS2 Error (System Bus Error)
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ULONGLONG Cbeal; // system bus error address register low.
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ULONGLONG Cbeah; // system bus error address register high.
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} GAMMA_CPU_ERROR, *PGAMMA_CPU_ERROR;
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//
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// Gamma Correctable and Uncorrectable Error Frame.
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//
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typedef struct _GAMMA_ERROR_FRAME {
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GAMMA_CPU_ERROR CpuError[4];
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SABLE_MEMORY_ERROR MemError[4];
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TX_ERROR_FRAME IoChipsetError;
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GAMMA_CONFIGURATION Configuration;
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} GAMMA_UNCORRECTABLE_FRAME, *PGAMMA_UNCORRECTABLE_FRAME,
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GAMMA_CORRECTABLE_FRAME, *PGAMMA_CORRECTABLE_FRAME;
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//
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// Rawhide Error Frame Definitions
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//
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//
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// CPU Daughter Card (CUD) Header
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//
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typedef struct _RAWHIDE_CUD_HEADER { // As Per Rawhide SPM
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ULONG ActiveCpus; // (0x00)
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ULONG HwRevision; // (0x04)
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UCHAR SystemSN[10]; // (0x08-0x11) Same as FRU System Serial Number
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UCHAR Reserved2[6]; // (0x12-0x17)
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UCHAR ModuleSN[10]; // (0x18-0x21) Module (processor) S/N, if available
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USHORT ModType; // (0x22)
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ULONG Reserved3; // (0x24)
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ULONG DisabledResources; // (0x28)
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UCHAR SystemRev[4]; // (0x2c) Same as FRU System Revision Level?
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} RAWHIDE_CUD_HEADER, *PRAWHIDE_CUD_HEADER;
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//
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// IOD Error Frame Valid Bits
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//
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// Corresponds to bitfields of ValidBits in the Iod Error Frame
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//
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typedef union _IOD_ERROR_FRAME_VALID_BITS {
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struct {
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ULONG IodBaseAddrValid: 1; // <0>
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ULONG WhoAmIValid: 1; // <1>
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ULONG PciRevValid: 1; // <2>
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ULONG CapCtrlValid: 1; // <3>
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ULONG HaeMemValid: 1; // <4>
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ULONG HaeIoValid: 1; // <5>
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ULONG IntCtrlValid: 1; // <6>
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ULONG IntReqValid: 1; // <7>
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ULONG IntMask0Valid: 1; // <8>
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ULONG IntMask1Valid: 1; // <9>
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ULONG McErr0Valid: 1; // <10>
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ULONG McErr1Valid: 1; // <11>
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ULONG CapErrValid: 1; // <12>
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ULONG PciErr1Valid: 1; // <13>
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ULONG MdpaStatValid: 1; // <14>
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ULONG MdpaSynValid: 1; // <15>
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ULONG MdpbStatValid: 1; // <16>
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ULONG MdpbSynValid: 1; // <17>
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};
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ULONG all;
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} IOD_ERROR_FRAME_VALID_BITS, *PIOD_ERROR_FRAME_VALID_BITS;
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//
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// IOD Error Frame
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//
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// N.B. Used in Uncorrectable *and* correctable error frames for
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||
// information on the IOD that recevied the machine check.
|
||
// It is uses as well in MC Bus snapshot (for each IOD) and Iod Register
|
||
// Subpacket.
|
||
// As far as I'm concerned, they IOD information is the same in each case.
|
||
// We can use the ValidBits field to optionally disable irrelevant
|
||
// fields.
|
||
//
|
||
|
||
typedef struct _IOD_ERROR_FRAME {
|
||
ULONGLONG BaseAddress; // (0x00)
|
||
ULONG WhoAmI; // (0x08)
|
||
IOD_ERROR_FRAME_VALID_BITS ValidBits; // (0x0c)
|
||
ULONG PciRevision; // (0x10)
|
||
ULONG CapCtrl; // (0x14)
|
||
ULONG HaeMem; // (0x18)
|
||
ULONG HaeIo; // (0x1c)
|
||
ULONG IntCtrl; // (0x20)
|
||
ULONG IntReq; // (0x24)
|
||
ULONG IntMask0; // (0x28)
|
||
ULONG IntMask1; // (0x2c)
|
||
ULONG McErr0; // (0x30)
|
||
ULONG McErr1; // (0x34)
|
||
ULONG CapErr; // (0x38)
|
||
ULONG Reserved0; // (0x3c)
|
||
ULONG PciErr1; // (0x40)
|
||
ULONG MdpaStat; // (0x44)
|
||
ULONG MdpaSyn; // (0x48)
|
||
ULONG MdpbStat; // (0x4c)
|
||
ULONG MdpbSyn; // (0x50)
|
||
ULONG Reserved1[3]; // (0x54-0x5f)
|
||
} IOD_ERROR_FRAME, *PIOD_ERROR_FRAME;
|
||
|
||
|
||
//
|
||
// Optional Snapshots for which headers or frames are defined below:
|
||
// PCI Bus Snapshot
|
||
// MC Bus Snapshot
|
||
// Memory Size Frame
|
||
// System Managment Frame
|
||
// ESC Frame
|
||
//
|
||
|
||
//
|
||
// Flags indicating which of the optional snapshots or frames are present
|
||
// in a correctable or uncorrectable error frame
|
||
//
|
||
|
||
typedef union _RAWHIDE_ERROR_SUBPACKET_FLAGS {
|
||
struct {
|
||
ULONGLONG Reserved0: 10; // <0:9> Reserved
|
||
ULONGLONG SysEnvPresent : 1; // <10>
|
||
ULONGLONG MemSizePreset : 1; // <11>
|
||
ULONGLONG Reserved1: 8; // <12:19> Reserved
|
||
ULONGLONG McBusPresent: 1; // <20>
|
||
ULONGLONG GcdBusPresent: 1; // <21>
|
||
ULONGLONG Reserved2: 8; // <22:29> Reserved
|
||
ULONGLONG IodSubpacketPresent: 1; // <30>
|
||
ULONGLONG PciSnapshotPresent: 1; // <31>
|
||
ULONGLONG EscSubpacketPresent: 1; // <32>
|
||
ULONGLONG Reserved3: 7; // <33:39> Reserved
|
||
ULONGLONG Iod2SubpacketPresent: 1; // <40> ???
|
||
ULONGLONG Pci2SnapshotPresent: 1; // <41> ???
|
||
};
|
||
ULONGLONG all;
|
||
} RAWHIDE_ERROR_SUBPACKET_FLAGS, *PRAWHIDE_ERROR_SUBPACKET_FLAGS;
|
||
|
||
|
||
//
|
||
// PCI Bus Snapshot Header
|
||
//
|
||
// Header is followed PCI_COMMON_CONFIG packets (256 bytes each) for each PCI
|
||
// device present in the system. Therefore,
|
||
// Length = sizeof (PCI_BUS_SNAPSHOT) + NumberOfNodes*sizeof(PCI_COMMON_CONFIG)
|
||
//
|
||
// N.B. PCI_COMMON_CONFIG is defined \nt\private\ntos\inc\pci.h
|
||
//
|
||
|
||
|
||
typedef struct _PCI_BUS_SNAPSHOT {
|
||
ULONG Length; // (0x00)
|
||
USHORT BusNumber; // (0x04)
|
||
USHORT NumberOfNodes; // (0x06)
|
||
//
|
||
// NumberOfNodes packets follow (0x08)
|
||
//
|
||
} PCI_BUS_SNAPSHOT, *PPCI_BUS_SNAPSHOT;
|
||
|
||
|
||
|
||
//
|
||
// MC Bus Snapshot Header
|
||
//
|
||
// Header is followed a IOD_ERROR_FRAME for each IOD on the system;
|
||
// Therefore,
|
||
// Length = sizeof (MC_BUS_SNAPSHOT) + NumberOfIods*sizeof(IOD_ERROR_FRAME)
|
||
//
|
||
|
||
typedef struct _MC_BUS_SNAPSHOT {
|
||
ULONG Length; // (0x00)
|
||
ULONG NumberOfIods; // (0x04)
|
||
ULONGLONG ReportingCpuBaseAddr; // (0x08)
|
||
|
||
//
|
||
// NumberOfIods packets follow (0x10)
|
||
//
|
||
|
||
} MC_BUS_SNAPSHOT, *PMC_BUS_SNAPSHOT;
|
||
|
||
|
||
//
|
||
// Memory Size Frame
|
||
//
|
||
|
||
typedef union _RAWHIDE_MEMORY_SIZE {
|
||
struct {
|
||
ULONGLONG MemorySize0: 8; // <0:7>
|
||
ULONGLONG MemorySize1: 8; // <8:15>
|
||
ULONGLONG MemorySize2: 8; // <16:23>
|
||
ULONGLONG MemorySize3: 8; // <24:31>
|
||
ULONGLONG Reserved: 24; // <32:55>
|
||
ULONGLONG MemorySize0Valid: 1; // <56>
|
||
ULONGLONG MemorySize1Valid: 1; // <57>
|
||
ULONGLONG MemorySize2Valid: 1; // <58>
|
||
ULONGLONG MemorySize3Valid: 1; // <59>
|
||
};
|
||
ULONGLONG all;
|
||
} RAWHIDE_MEMORY_SIZE, *PRAWHIDE_MEMORY_SIZE;
|
||
|
||
|
||
//
|
||
// System Managment Frame
|
||
//
|
||
|
||
typedef struct _RAWHIDE_SYSTEM_MANAGEMENT_FRAME {
|
||
ULONGLONG SystemEnvironment; // (0x00)
|
||
ULONG Elcr2; // (0x08) (see IOD_ELCR2 in iod.h)
|
||
ULONG Reserved0; // (0x0c)
|
||
} SYSTEM_MANAGEMENT_FRAME, *PSYSTEM_MANAGEMENT_FRAME;
|
||
|
||
typedef union _RAWHIDE_SYSTEM_ENVIRONMENT {
|
||
struct {
|
||
ULONGLONG FanFailReg: 8; // <0:7> I2C Fain Fail Register
|
||
ULONGLONG SensorReg1: 8; // <8:15> I2C Sensor Register 1
|
||
ULONGLONG OpcControl: 8; // <16:23> I2C OPC Control
|
||
ULONGLONG SensorReg2: 8; // <24:31> I2C Sensor Register 2
|
||
ULONGLONG Reserved: 24; // <32:55> I2C Sensor Register 1
|
||
ULONGLONG FanFailValid: 1; // <56>
|
||
ULONGLONG SensorReg1Valid: 1; // <57>
|
||
ULONGLONG OpcControlValid: 1; // <58>
|
||
ULONGLONG SensorReg2Valid: 1; // <59>
|
||
};
|
||
ULONGLONG all;
|
||
} RAWHIDE_SYSTEM_ENVIRONMENT, *PRAWHIDE_SYSTEM_ENVIRONMENT;
|
||
|
||
|
||
//
|
||
// ESC Frame
|
||
//
|
||
// This isn't just and ESC frame. EISA Id information is also contained herein.
|
||
//
|
||
// N.B. "index" refers to an indexed config ESC register accessed at index/data
|
||
// ports 0x22/0x23.
|
||
//
|
||
|
||
|
||
typedef struct _ESC_FRAME {
|
||
UCHAR Id[4]; // (0x00) "ESC\0"
|
||
ULONG ByteCount; // (0x04) ???
|
||
UCHAR EscId; // (0x08) ESC ID Register (index 0x02)
|
||
UCHAR Filler0[7]; // (0x09-0x0f)
|
||
UCHAR Rid; // (0x0c) Revision Id (index 0x08)
|
||
UCHAR Filler1[3]; // (0x0d-0x0f)
|
||
UCHAR ModeSel; // (0x10) Mode Select Reg (index 0x40)
|
||
UCHAR Filler2[3]; // (0x11-0x13)
|
||
UCHAR EisaId[4]; // (0x14-0x17) EisaId of devices in EISA Slots
|
||
UCHAR SgRba; // (0x18) S-G Reloate Base Addr Reg (index 57)
|
||
UCHAR Filler3[3]; // (0x19-0x1b)
|
||
UCHAR Pirq[4]; // (0x1c-0x1f) PIRQ Route Ctrl (index 0x60-0x63)
|
||
UCHAR NmiSc; // (0x20) NMI Status & Ctrl (port 0x61)
|
||
UCHAR Filler4[3]; // (0x21-0x23)
|
||
UCHAR NmiEsc; // (0x24) NMI Ext. Status & Ctrl (port 0x461)
|
||
UCHAR Filler5[3]; // (0x25-0x27)
|
||
UCHAR LEisaMg; // (0x28) Last EISA Master Granted (port 0x464)
|
||
UCHAR Filler6[3]; // (0x29-0x2b)
|
||
} ESC_FRAME, *PESC_FRAME;
|
||
|
||
|
||
//
|
||
// Rawhide Correctable (Soft) Error Frame
|
||
// Rawhide Uncorrectable (Hard) Error Frame
|
||
//
|
||
|
||
#define RAWHIDE_UNCORRECTABLE_FRAME_REVISION 0x10 // V1.0
|
||
#define RAWHIDE_CORRECTABLE_FRAME_REVISION 0x10 // V1.0
|
||
|
||
typedef struct _RAWHIDE_UNCORRECTABLE_FRAME {
|
||
ULONG Revision; // (0x00)
|
||
ULONG WhoAmI; // (0x04)
|
||
RAWHIDE_ERROR_SUBPACKET_FLAGS ErrorSubpacketFlags; // (0x08)
|
||
RAWHIDE_CUD_HEADER CudHeader; // (0x10-0x4f)
|
||
MC_BUS_SNAPSHOT McBusSnapshot; // (0x50-0x5f)
|
||
|
||
//
|
||
// Uncorrectable Error Frame will have:
|
||
// a) two (Dodge) or four (Durango) IOD_ERROR_FRAMEs (0x60 - ???)
|
||
//
|
||
// b) Optional Error Subpackets as per ErrorSubpacketFlags
|
||
//
|
||
|
||
} RAWHIDE_UNCORRECTABLE_FRAME, *PRAWHIDE_UNCORRECTABLE_FRAME;
|
||
|
||
typedef struct _RAWHIDE_CORRECTABLE_FRAME {
|
||
ULONG Revision; // (0x00)
|
||
ULONG WhoAmI; // (0x04)
|
||
RAWHIDE_ERROR_SUBPACKET_FLAGS ErrorSubpacketFlags; // (0x08)
|
||
RAWHIDE_CUD_HEADER CudHeader; // (0x10-0x4f)
|
||
IOD_ERROR_FRAME IodErrorFrame; // (0x50-0xaf)
|
||
|
||
//
|
||
// Correctable Error will always have only
|
||
// one IOD in the McBusSnapshot, that of the IOD with
|
||
// the correctable error.
|
||
//
|
||
|
||
} RAWHIDE_CORRECTABLE_FRAME, *PRAWHIDE_CORRECTABLE_FRAME;
|
||
|
||
|
||
#endif //ERRPLAT_H
|