476 lines
8.2 KiB
C
476 lines
8.2 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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ev5cache.c
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Abstract:
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This file contains the routines for managing the caches on machines
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based on the DECchip 21164 microprocessor (aka EV5).
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EV5 has primary I and D caches of 8KB each, Dcache is write-through.
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EV5 also contains a 96K, 3-way set associative, write-back secondary cache.
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Many EV5 systems will also have an external 3rd level backup cache.
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The data caches (internal and external) must be kept coherent by the
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hardware. Instruction cache coherency is maintained by software.
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EV5 has a write buffer which contains 6 32-byte entries, which
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must be flushable before DMA operations. The MB instruction is
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used to accomplish this.
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There is no coloring support on EV5, so Color operations are
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null. Zero page is implemented in ev5mem.s Copy page is not
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special because we lack coloring.
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Author:
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Miche Baker-Harvey (miche) 29-May-1992 (EV4 version)
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Steve Brooks 30-Jun-1994 (EV5 version)
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Joe Notarangelo 30-Jun-1994 (EV5 version)
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Revision History:
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--*/
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#include "halp.h"
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VOID
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HalFlushDcache (
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IN BOOLEAN AllProcessors
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);
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//
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// Cache and write buffer flush functions.
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//
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VOID
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HalChangeColorPage (
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IN PVOID NewColor,
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IN PVOID OldColor,
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IN ULONG PageFrame
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)
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/*++
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Routine Description:
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This function changes the color of a page if the old and new colors
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do not match. DECchip 21064-based machines do not have page coloring, and
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therefore, this function performs no operation.
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Arguments:
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NewColor - Supplies the page aligned virtual address of the
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new color of the page to change.
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OldColor - Supplies the page aligned virtual address of the
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old color of the page to change.
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pageFrame - Supplies the page frame number of the page that
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is changed.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalFlushDcachePage (
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IN PVOID Color,
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IN ULONG PageFrame,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes (invalidates) up to a page of data from the
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data cache.
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Arguments:
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Color - Supplies the starting virtual address and color of the
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data that is flushed.
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PageFrame - Supplies the page frame number of the page that
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is flushed.
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Length - Supplies the length of the region in the page that is
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flushed.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalFlushIoBuffers (
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IN PMDL Mdl,
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IN BOOLEAN ReadOperation,
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IN BOOLEAN DmaOperation
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)
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/*++
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Routine Description:
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This function flushes the I/O buffer specified by the memory descriptor
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list from the data cache on the current processor.
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Arguments:
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Mdl - Supplies a pointer to a memory descriptor list that describes the
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I/O buffer location.
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ReadOperation - Supplies a boolean value that determines whether the I/O
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operation is a read into memory.
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DmaOperation - Supplies a boolean value that determines whether the I/O
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operation is a DMA operation.
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Return Value:
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None.
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--*/
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{
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//
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// The Dcache coherency is maintained in hardware. The Icache coherency
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// is maintained by invalidating the istream on page read operations.
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//
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HalpMb(); // synchronize this processors view of memory
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if (ReadOperation) {
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HalpMb(); // not issued until previous mb completes
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if (Mdl->MdlFlags & MDL_IO_PAGE_READ) {
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//
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// The operation is a page read, thus the istream must
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// be flushed.
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//
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HalpImb();
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}
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}
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}
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VOID
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HalPurgeDcachePage (
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IN PVOID Color,
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IN ULONG PageFrame,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function purges (invalidates) up to a page of data from the
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data cache.
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Arguments:
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Color - Supplies the starting virtual address and color of the
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data that is purged.
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PageFrame - Supplies the page frame number of the page that
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is purged.
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Length - Supplies the length of the region in the page that is
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purged.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalPurgeIcachePage (
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IN PVOID Color,
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IN ULONG PageFrame,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function purges (invalidates) up to a page fo data from the
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instruction cache.
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Arguments:
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Color - Supplies the starting virtual address and color of the
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data that is purged.
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PageFrame - Supplies the page frame number of the page that
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is purged.
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Length - Supplies the length of the region in the page that is
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purged.
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Return Value:
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None.
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--*/
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{
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//
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// The call to HalpImb calls PAL to flush the Icache, which ensures that
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// any stale hits will be invalidated
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//
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HalpImb();
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}
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VOID
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HalSweepDcache (
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VOID
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)
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/*++
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Routine Description:
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This function sweeps (invalidates) the entire data cache.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalSweepDcacheRange (
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes the specified range of addresses from the data
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cache on the current processor.
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Arguments:
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BaseAddress - Supplies the starting physical address of a range of
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physical addresses that are to be flushed from the data cache.
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Length - Supplies the length of the range of physical addresses
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that are to be flushed from the data cache.
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Return Value:
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None.
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--*/
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{
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return;
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}
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VOID
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HalSweepIcache (
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VOID
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)
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/*++
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Routine Description:
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This function sweeps (invalidates) the entire instruction cache.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// The call to HalpImb calls PAL to flush the Icache, which ensures that
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// any stale hits will be invalidated
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//
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HalpImb();
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return;
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}
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VOID
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HalSweepIcacheRange (
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IN PVOID BaseAddress,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes the specified range of addresses from the
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instruction cache on the current processor.
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Arguments:
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BaseAddress - Supplies the starting physical address of a range of
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physical addresses that are to be flushed from the instruction cache.
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Length - Supplies the length of the range of physical addresses
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that are to be flushed from the instruction cache.
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Return Value:
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None.
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--*/
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{
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//
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// The call to HalpImb calls PAL to flush the Icache, which ensures that
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// any stale hits will be invalidated
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//
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HalpImb;
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}
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VOID
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KeFlushWriteBuffer (
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VOID
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)
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{
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//
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// We flush the write buffer by doing a series of memory
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// barrier operations, the flush method is specific to the 21164.
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//
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HalpMb();
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HalpMb();
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return;
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}
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VOID
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KeFlushDcache (
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IN BOOLEAN AllProcessors,
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IN PVOID BaseAddress OPTIONAL,
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IN ULONG Length
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)
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/*++
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Routine Description:
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This function flushes the data cache on all processors that are currently
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running threads which are children of the current process or flushes the
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data cache on all processors in the host configuration.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which data
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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UNREFERENCED_PARAMETER(BaseAddress);
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UNREFERENCED_PARAMETER(Length);
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HalFlushDcache(AllProcessors);
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return;
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}
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VOID
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HalFlushDcache (
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IN BOOLEAN AllProcessors
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)
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/*++
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Routine Description:
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This function flushes the data cache on all processors that are currently
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running threads which are children of the current process or flushes the
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data cache on all processors in the host configuration.
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Arguments:
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AllProcessors - Supplies a boolean value that determines which data
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caches are flushed.
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Return Value:
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None.
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--*/
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{
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//
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// Sweep (index/writeback/invalidate) the data cache.
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//
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HalSweepDcache();
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return;
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}
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ULONG
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HalGetDmaAlignmentRequirement (
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VOID
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)
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/*++
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Routine Description:
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This function returns the alignment requirements for DMA transfers on
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host system.
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Arguments:
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None.
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Return Value:
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The DMA alignment requirement is returned as the fucntion value.
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--*/
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{
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return 8;
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}
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