85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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gru.h
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Abstract:
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This file defines the structures and definitions for the GRU ASIC.
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Author:
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Steve Brooks 7-July-1994
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef _GRUH_
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#define _GRUH_
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//
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// Define locations of the GRU ASIC registers
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//
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#define GRU_CSRS_PHYSICAL ((ULONGLONG)0x8780000000)
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#define GRU_CSRS_QVA HAL_MAKE_QVA(GRU_CSRS_PHYSICAL)
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#define GRU_CACHECNFG_CSRS_PHYSICAL ((ULONGLONG)0x8780000200)
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#define GRU_CACHECNFG_CSRS_QVA HAL_MAKE_QVA(GRU_CSRS_PHYSICAL)
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//
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// Define various masks for the GRU registers
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//
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#define GRU_ENABLE_EISA_INT 0x80000000
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#define GRU_SET_LEVEL_INT 0x00000000
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#define GRU_SET_LOW_INT 0x8F000000
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#define GRU_PCI_MASK_INT 0x000FFFFF
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#define GRU_EISA_MASK_INT 0x80000000
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//
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// Define GRU Interrupt register access structure:
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//
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typedef struct _GRU_INTERRUPT_CSRS{
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UCHAR IntReq; // (00) Interrupt Request Register
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UCHAR Filler1; // (20)
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UCHAR IntMask; // (40) Interrupt Mask Register
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UCHAR Filler2; // (60)
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UCHAR IntEdge; // (80) Edge/Level Interrupt Select
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UCHAR Filler3; // (a0)
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UCHAR IntHiLo; // (c0) Active High/Low select register
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UCHAR Filler4; // (e0)
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UCHAR IntClear; // (100) Interrupt Clear register
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} GRU_INTERRUPT_CSRS, *PGRU_INTERRUPT_CSRS;
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//
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// Define GRU cache register structure.
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//
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typedef union _GRU_CACHECNFG{
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struct{
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ULONG Reserved0 : 4; //
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ULONG ClockDivisor: 4; // Clock divisor for EV5.
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ULONG Reserved1 : 3; //
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ULONG CacheSpeed : 2; // SRAM cache access time.
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ULONG CacheSize : 3; // SRAM cache size.
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ULONG Mmb0Config : 4; // Presence and type of MMB0.
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ULONG Reserved2 : 4; //
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ULONG Mmb1Config : 4; // Presence and type of MMB1.
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ULONG Reserved3 : 4; //
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};
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ULONG all;
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} GRU_CACHECNFG, *PGRU_CACHECNFG;
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#endif // _GRUH_
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