761 lines
20 KiB
C
761 lines
20 KiB
C
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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t2.c
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Abstract:
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This module implements functions that are specific to the T2 chip.
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The T2 chip is a system support chip that bridges between the
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CBUS2 and the PCI bus.
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Author:
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Joe Notarangelo 18-Oct-1993
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Steve Jenness 18-Oct-1993
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Environment:
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Kernel mode
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Revision History:
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Steve Brooks 30-Dec-1994
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Remove sable specific references and move to common halalpha directory
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--*/
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#include "halp.h"
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extern ULONG HalDisablePCIParityChecking;
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#ifdef HALDBG
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ULONG T2Debug;
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VOID
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DumpT2(
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VOID
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);
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VOID
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DumpT4(
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VOID
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);
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#define DebugDumpT2(DebugPrintLevel) \
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if (DebugPrintLevel <= T2Debug) \
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DumpT2()
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#else //HALDBG
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#define DebugDumpT2(a)
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#endif //HALDBG
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VOID
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HalpT2InitializeSfwWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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T2_WINDOW_NUMBER WindowNumber
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)
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/*++
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Routine Description:
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Initialize the DMA Control software window registers for the specified
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DMA Window.
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Arguments:
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WindowRegisters - Supplies a pointer to the software window control.
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WindowNumber - Supplies the window number initialized. (0 = Isa Dma
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Window, 1 = Master Dma Window).
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Return Value:
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None.
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--*/
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{
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switch( WindowNumber ){
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//
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// The ISA DMA Window.
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//
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case T2IsaWindow:
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WindowRegisters->WindowBase = (PVOID)ISA_DMA_WINDOW_BASE;
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WindowRegisters->WindowSize = ISA_DMA_WINDOW_SIZE;
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WindowRegisters->TranslatedBaseRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Tbase1;
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WindowRegisters->WindowBaseRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Wbase1;
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WindowRegisters->WindowMaskRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Wmask1;
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WindowRegisters->WindowTbiaRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Iocsr;
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WindowRegisters->TranslatedBaseRegister[1] = NULL;
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WindowRegisters->WindowBaseRegister[1] = NULL;
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WindowRegisters->WindowMaskRegister[1] = NULL;
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WindowRegisters->WindowTbiaRegister[1] = NULL;
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break;
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case T2MasterWindow:
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WindowRegisters->WindowBase = (PVOID)MASTER_DMA_WINDOW_BASE;
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WindowRegisters->WindowSize = MASTER_DMA_WINDOW_SIZE;
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WindowRegisters->TranslatedBaseRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Tbase2;
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WindowRegisters->WindowBaseRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Wbase2;
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WindowRegisters->WindowMaskRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Wmask2;
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WindowRegisters->WindowTbiaRegister[0] =
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&((PT2_CSRS)(T2_CSRS_QVA))->Iocsr;
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WindowRegisters->TranslatedBaseRegister[1] =
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&((PT2_CSRS)(T4_CSRS_QVA))->Tbase2;
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WindowRegisters->WindowBaseRegister[1] =
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&((PT2_CSRS)(T4_CSRS_QVA))->Wbase2;
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WindowRegisters->WindowMaskRegister[1] =
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&((PT2_CSRS)(T4_CSRS_QVA))->Wmask2;
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WindowRegisters->WindowTbiaRegister[1] =
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&((PT2_CSRS)(T4_CSRS_QVA))->Iocsr;
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break;
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default:
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#if HALDBG
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DbgPrint( "T2InitializeSfwWindow: Bad Window Number = %x\n",
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WindowNumber );
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#endif //HALDBG
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break;
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}
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return;
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}
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VOID
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HalpT2ProgramDmaWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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PVOID MapRegisterBase
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)
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/*++
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Routine Description:
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Program the control windows in the hardware so that DMA can be started
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to the DMA window.
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Arguments:
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WindowRegisters - Supplies a pointer to the software window register
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control structure.
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MapRegisterBase - Supplies the logical address of the scatter/gather
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array in system memory.
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Return Value:
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None.
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--*/
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{
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T2_WBASE PciBase;
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T2_WMASK PciMask;
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T2_TBASE Tbase;
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PciBase.all = 0;
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PciBase.EnablePciWindow = 1;
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PciBase.EnableScatterGather = 1;
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PciBase.PciWindowStartAddress = (ULONG)(WindowRegisters->WindowBase) >> 20;
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PciBase.PciWindowEndAddress =
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((ULONG)(WindowRegisters->WindowBase) +
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WindowRegisters->WindowSize - 1) >> 20;
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PciMask.all = 0;
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PciMask.PciWindowMask = (WindowRegisters->WindowSize >> 20) - 1;
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Tbase.all = 0;
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Tbase.TranslatedBaseAddress = (ULONG)(MapRegisterBase) >> 10;
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//
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// Dump the T2 registers.
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//
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DebugDumpT2(5);
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//
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// Clear the window base, temporarily disabling transactions to this
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// DMA window.
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//
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WRITE_T2_REGISTER( WindowRegisters->WindowBaseRegister[0], (ULONGLONG)0 );
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//
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// Now program the window by writing the translated base, then the size
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// of the window in the mask register and finally the window base,
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// enabling both the window and scatter gather.
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//
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WRITE_T2_REGISTER( WindowRegisters->TranslatedBaseRegister[0],
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*(PULONGLONG)&Tbase );
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WRITE_T2_REGISTER( WindowRegisters->WindowMaskRegister[0],
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*(PULONGLONG)&PciMask );
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WRITE_T2_REGISTER( WindowRegisters->WindowBaseRegister[0],
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*(PULONGLONG)&PciBase );
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// smjfix - Turn on Hole 1 and 2 to make access to
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// Eisa memory space work. This is currently used to
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// to allow access to the Qvision frame buffer at 4Mbytes.
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// Note that the StartAddress and EndAddress need to be
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// shifted by 1 bit (in contrast to the T2 spec).
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// Currently memory devices on Sable have to be 0-16Mbytes or
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// above 2Gbytes.
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{
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T2_HBASE Hbase;
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Hbase.all = 0;
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Hbase.HoleStartAddress = 0x40 << 1; // 4 Mbytes
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Hbase.HoleEndAddress = 0x4f << 1; // 5 Mbytes - 1
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Hbase.Hole1Enable = 1;
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Hbase.Hole2Enable = 1;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Hbase,
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*(PULONGLONG)&Hbase );
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}
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#if defined(XIO_PASS1) || defined(XIO_PASS2)
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//
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// If the external I/O module is present and this is *not* the ISA
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// DMA window, initialize the T4 similarly.
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//
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if( HalpXioPresent && WindowRegisters->WindowBaseRegister[1] != NULL ) {
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#if HALDBG
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DumpT4();
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#endif
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//
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// Clear the window base, temporarily disabling transactions to this
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// DMA window.
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//
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WRITE_T2_REGISTER( WindowRegisters->WindowBaseRegister[1],
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(ULONGLONG)0 );
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//
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// Now program the window by writing the translated base, then the size
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// of the window in the mask register and finally the window base,
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// enabling both the window and scatter gather.
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//
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WRITE_T2_REGISTER( WindowRegisters->TranslatedBaseRegister[1],
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*(PULONGLONG)&Tbase );
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WRITE_T2_REGISTER( WindowRegisters->WindowMaskRegister[1],
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*(PULONGLONG)&PciMask );
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WRITE_T2_REGISTER( WindowRegisters->WindowBaseRegister[1],
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*(PULONGLONG)&PciBase );
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//
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// The external I/O module does not have a co-resident EISA/ISA
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// bus, therefore, no holes are necessary.
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//
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WRITE_T2_REGISTER( &((PT2_CSRS)(T4_CSRS_QVA))->Hbase,
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(ULONGLONG)0 );
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#if HALDBG
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DumpT4();
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#endif
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}
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#endif
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//
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// Flush and enable the translation buffer inside of the T2.
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// Since the TLB is maintained by bus snooping, this should be the
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// only time a flush is needed.
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//
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{
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ULONGLONG Value;
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T2_IOCSR Iocsr;
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Value = READ_T2_REGISTER(&((PT2_CSRS)(T2_CSRS_QVA))->Iocsr);
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Iocsr = *(PT2_IOCSR)&Value;
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Iocsr.EnableTlb = 0;
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Iocsr.FlushTlb = 1;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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Iocsr.EnableTlb = 1;
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Iocsr.FlushTlb = 0;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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#if defined(XIO_PASS1) || defined(XIO_PASS2)
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if( HalpXioPresent ) {
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Value = READ_T2_REGISTER(&((PT2_CSRS)(T4_CSRS_QVA))->Iocsr);
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Iocsr = *(PT2_IOCSR)&Value;
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Iocsr.EnableTlb = 0;
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Iocsr.FlushTlb = 1;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T4_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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Iocsr.EnableTlb = 0;
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Iocsr.FlushTlb = 0;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T4_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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#if HALDBG
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DumpT4();
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#endif
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}
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#endif
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}
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//
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// Dump the T2 registers.
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//
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DebugDumpT2(5);
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return;
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}
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VOID
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HalpT2InvalidateTLB(
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PWINDOW_CONTROL_REGISTERS WindowRegisters
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)
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/*++
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Routine Description:
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Invalidate the DMA Scatter/Gather TLB in the T2. This routine
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is called when initializing the window registers. It is *not*
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called by HAL_INVALIDATE_TRANSLATIONS because invalidating the
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TLB when DMAs are in progress doesn't work on the T2.
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There is a single TLB in the T2; the WindowRegisters argument is
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ignored.
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Arguments:
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WindowRegisters - Supplies a pointer to the software window register
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control structure.
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Return Value:
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None.
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--*/
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{
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ULONGLONG Value;
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T2_IOCSR Iocsr;
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#if 0
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// Pass2 appears to be broken also.
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#ifndef T2PASS1ONLY
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//
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// If the T2 is a Pass2 or later, flush and enable the TLB.
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//
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Value = READ_T2_REGISTER(&((PT2_CSRS)(T2_CSRS_QVA))->Iocsr);
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Iocsr = *(PT2_IOCSR)&Value;
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if (Iocsr.T2RevisionNumber != 0) {
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Iocsr.FlushTlb = 1;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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Iocsr.EnableTlb = 1;
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Iocsr.FlushTlb = 0;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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}
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#if defined(XIO_PASS1) || defined(XIO_PASS2)
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//
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// Invalidate the T4's TLB...
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//
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if( HalpXioPresent ){
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Value = READ_T2_REGISTER(&((PT2_CSRS)(T4_CSRS_QVA))->Iocsr);
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Iocsr = *(PT2_IOCSR)&Value;
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Iocsr.FlushTlb = 1;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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Iocsr.EnableTlb = 0;
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Iocsr.FlushTlb = 0;
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WRITE_T2_REGISTER( &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr,
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*(PULONGLONG)&Iocsr );
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}
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#endif
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#endif //T2PASS1ONLY
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#endif //0
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}
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#if HALDBG
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VOID
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DumpT2(
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VOID
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)
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/*++
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Routine Description:
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Read the interesting T2 registers and print them to the debug port.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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PVOID RegisterQva;
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PVOID TestQva;
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ULONGLONG Value;
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ULONG LongValue;
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T2_TDR Tdr;
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// DbgPrint( "Dumping the T2 registers, " );
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#if 0
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//
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// This code tests whether the windows and holes allow access to
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// the address in I/O memory space set in PhysicalAddress.
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// See also the companion code at the end of this routine.
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//
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{
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ULONG AddressSpace;
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PHYSICAL_ADDRESS PhysicalAddress;
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AddressSpace = 0;
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PhysicalAddress.LowPart = 0xD0000; // DE422
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// PhysicalAddress.LowPart = 0x2200000; // 34Mbytes
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// PhysicalAddress.LowPart = 0x0400000; // 4Mbytes
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PhysicalAddress.HighPart = 0;
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HalTranslateBusAddress( Isa, 0, PhysicalAddress, &AddressSpace, &TestQva );
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LongValue = READ_REGISTER_ULONG( TestQva );
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DbgPrint( "TestQva = %lx, Value = %x, writing 0xa5a5a5a5..\n",
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TestQva, LongValue );
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LongValue = 0xa5a5a5a5;
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WRITE_REGISTER_ULONG( TestQva, LongValue );
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LongValue = READ_REGISTER_ULONG( TestQva );
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DbgPrint( "TestQva = %lx, Value = %x\n", TestQva, LongValue );
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}
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#endif // 0
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#if 0
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Iocsr;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Iocsr = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Ivrpr;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Ivrpr = %Lx\n", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Hae0_1;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Hae0_1 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Hae0_2;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Hae0_2 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Hbase;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Hbase = %Lx\n", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Wbase1;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Wbase1 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Wmask1;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Wmask1 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tbase1;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Tbase1 = %Lx\n", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Wbase2;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Wbase2 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Wmask2;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Wmask2 = %Lx, ", Value );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tbase2;
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Value = READ_T2_REGISTER( RegisterQva );
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DbgPrint( "Tbase2 = %Lx\n", Value );
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#endif // 0
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr0;
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Value = READ_T2_REGISTER( RegisterQva );
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Tdr = *(PT2_TDR)&Value;
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DbgPrint( "Tdr0 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
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RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr1;
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Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr1 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr2 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr3 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr4 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr5;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr5 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr6;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr6 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T2_CSRS_QVA))->Tdr7;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr7 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
#if 0
|
||
LongValue = READ_REGISTER_ULONG( TestQva );
|
||
DbgPrint( "TestQva = %lx, Value = %x, writing 0xc3c3c3c3..\n",
|
||
TestQva, LongValue );
|
||
LongValue = 0xc3c3c3c3;
|
||
WRITE_REGISTER_ULONG( TestQva, LongValue );
|
||
LongValue = READ_REGISTER_ULONG( TestQva );
|
||
DbgPrint( "TestQva = %lx, Value = %x\n", TestQva, LongValue );
|
||
#endif // 0
|
||
|
||
// DbgPrint( "--end T2 dump\n\n" );
|
||
|
||
return;
|
||
|
||
}
|
||
|
||
#endif //HALDBG
|
||
|
||
#if HALDBG && defined(XIO_PASS1) || defined(XIO_PASS2)
|
||
|
||
VOID
|
||
DumpT4(
|
||
VOID
|
||
)
|
||
/*++
|
||
|
||
Routine Description:
|
||
|
||
Read the interesting T2 registers and print them to the debug port.
|
||
|
||
Arguments:
|
||
|
||
None.
|
||
|
||
Return Value:
|
||
|
||
None.
|
||
|
||
--*/
|
||
{
|
||
PVOID RegisterQva;
|
||
ULONGLONG Value;
|
||
ULONG LongValue;
|
||
T2_TDR Tdr;
|
||
|
||
if( !HalpXioPresent ){
|
||
DbgPrint( "XIO module not present.\n" );
|
||
return;
|
||
}
|
||
|
||
DbgPrint( "Dumping the T4 registers:\n" );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Iocsr;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Iocsr = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Ivrpr;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Ivrpr = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Hae0_1;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Hae0_1 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Hae0_2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Hae0_2 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Hae0_3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Hae0_3 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Hae0_4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Hae0_4 = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Hbase;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Hbase = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wbase1;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wbase1 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wmask1;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wmask1 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tbase1;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Tbase1 = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wbase2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wbase2 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wmask2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wmask2 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tbase2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Tbase2 = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wbase3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wbase3 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wmask3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wmask3 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tbase3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Tbase3 = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wbase4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wbase4 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Wmask4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Wmask4 = %Lx, ", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tbase4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
DbgPrint( "Tbase4 = %Lx\n", Value );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr0;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr0 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr1;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr1 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr2;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr2 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr3;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr3 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr4;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr4 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr5;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr5 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr6;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr6 PFN=%x, V=%x, Tag=%x, ", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
RegisterQva = &((PT2_CSRS)(T4_CSRS_QVA))->Tdr7;
|
||
Value = READ_T2_REGISTER( RegisterQva );
|
||
Tdr = *(PT2_TDR)&Value;
|
||
DbgPrint( "Tdr7 PFN=%x, V=%x, Tag=%x\n", Tdr.Pfn, Tdr.Valid, Tdr.Tag );
|
||
|
||
DbgPrint( "--end T4 dump\n\n" );
|
||
}
|
||
|
||
#endif //HALDBG
|