551 lines
15 KiB
C
551 lines
15 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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t2.h
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Abstract:
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This file defines the structures and definitions describing the
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T2 chipset
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Author:
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Steve Brooks 28-Dec 1994
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Environment:
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Kernel mode
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Revision History:
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Extracted from sable.h to be platform independent for sable, gamma & lynx
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--*/
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#ifndef _T2H_
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#define _T2H_
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//
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// N.B. The structure below defines the address offsets of the control
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// registers when used with the base QVA. It does NOT define the
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// size or structure of the individual registers.
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//
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typedef struct _T2_CSRS {
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UCHAR Iocsr; // I/O Control/Status Register
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UCHAR Cerr1; // CBUS Error Register 1
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UCHAR Cerr2; // CBUS Error Register 2
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UCHAR Cerr3; // CBUS Error Register 3
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UCHAR Perr1; // PCI Error Register 1
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UCHAR Perr2; // PCI Error Register 2
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UCHAR Pscr; // PCI Special Cycle Register
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UCHAR Hae0_1; // High Address Extension Register 1
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UCHAR Hae0_2; // High Address Extension Register 2
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UCHAR Hbase; // PCI Hole Base Register
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UCHAR Wbase1; // Window Base Register 1
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UCHAR Wmask1; // Window Mask Register 1
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UCHAR Tbase1; // Translated Base Register 1
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UCHAR Wbase2; // Window Base Register 2
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UCHAR Wmask2; // Window Mask Register 2
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UCHAR Tbase2; // Translated Base Register 2
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UCHAR Tlbbr; // TLB Bypass Register
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UCHAR Ivrpr; // IVR Passive Release Register
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UCHAR Hae0_3; // High Address Extension Register 3
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UCHAR Hae0_4; // High Address Extension Register 4
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UCHAR Wbase3; // Window Base Register 3 (T3/T4)
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UCHAR Wmask3; // Window Mask Register 3 (T3/T4)
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UCHAR Tbase3; // Translated Base Register 3 (T3/T4)
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UCHAR filler0;
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UCHAR Tdr0; // TLB Data Register 0
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UCHAR Tdr1; // TLB Data Register 1
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UCHAR Tdr2; // TLB Data Register 2
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UCHAR Tdr3; // TLB Data Register 3
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UCHAR Tdr4; // TLB Data Register 4
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UCHAR Tdr5; // TLB Data Register 5
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UCHAR Tdr6; // TLB Data Register 6
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UCHAR Tdr7; // TLB Data Register 7
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UCHAR Wbase4; // Window Base Register 4 (T3/T4)
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UCHAR Wmask4; // Window Mask Register 4 (T3/T4)
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UCHAR Tbase4; // Translated Base Register 4 (T3/T4)
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UCHAR Air; // Address Indirection Register (T3/T4)
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UCHAR Var; // Vector Access Register (T3/T4)
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UCHAR Dir; // Data Indirection Register (T3/T4)
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UCHAR Ice; // IC Enable Register (T3/T4)
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} T2_CSRS, *PT2_CSRS;
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//
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// Define formats of useful T2 registers.
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//
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typedef union _T2_IOCSR {
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struct {
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ULONG EnableReadIoReq: 1; // 00 - P2 Defunct, MBZ
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ULONG EnableLoopBack: 1; // 01
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ULONG EnableStateMachineVisibility: 1; // 02
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ULONG PciDriveBadParity: 1; // 03
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ULONG Mba0: 1; // 04
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ULONG Mba1: 1; // 05
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ULONG PciInterrupt: 1; // 06
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ULONG EnableTlbErrorCheck: 1; // 07
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ULONG EnableCxAckCheckForDma: 1; // 08
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ULONG EnableDenseWrap: 1; // 09
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ULONG CbusEnableExclusiveExchange: 1; // 10
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ULONG Pci64Enable: 1; // 11
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ULONG CbusCAWriteWrongParity0: 1; // 12
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ULONG CbusCAWriteWrongParity2: 1; // 13
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ULONG CbusCADataWriteWrongParityEven: 1; // 14
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ULONG Mba5: 1; // 15
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ULONG Mba6: 1; // 16 - P2 Power Supply Error
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ULONG Mba7: 1; // 17
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ULONG Mba2: 1; // 18
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ULONG Mba3: 1; // 19
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ULONG PciDmaWriteWrongParityHW1: 1; // 20
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ULONG PciDmaWriteWrongParityHW0: 1; // 21
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ULONG PciBusReset: 1; // 22
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ULONG PciInterfaceReset: 1; // 23
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ULONG EnableCbusErrorInterrupt: 1; // 24
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ULONG EnablePciMemorySpace: 1; // 25
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ULONG EnableTlb: 1; // 26
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ULONG EnableHogMode: 1; // 27
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ULONG FlushTlb: 1; // 28
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ULONG EnableCbusParityCheck: 1; // 29
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ULONG CbusInterfaceReset: 1; // 30
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ULONG EnablePciLock: 1; // 31
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ULONG EnableCbusBackToBackCycle: 1; // 32
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ULONG T2RevisionNumber: 3; // 33
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ULONG StateMachineVisibilitySelect: 3; // 36
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ULONG Mba4: 1; // 39
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ULONG EnablePassiveRelease: 1; // 40
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ULONG EnablePciRdp64: 1; // 41 (T4)
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ULONG EnablePciAp64: 1; // 42 (T4)
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ULONG EnablePciWdp64: 1; // 43 (T4)
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ULONG CbusCAWriteWrongParity1: 1; // 44
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ULONG CbusCAWriteWrongParity3: 1; // 45
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ULONG CbusCADataWriteWrongParityOdd: 1; // 46
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ULONG T2T4Status: 1; // 47
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ULONG EnablePpc1: 1; // 48 (T3/T4)
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ULONG EnablePpc2: 1; // 49 (T3/T4)
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ULONG EnablePciStall: 1; // 50 (T3/T4)
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ULONG Mbz0: 1; // 51
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ULONG PciReadMultiple: 1; // 52
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ULONG PciWriteMultiple: 1; // 53
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ULONG ForcePciRdpeDetect: 1; // 54
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ULONG ForcePciApeDetect: 1; // 55
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ULONG ForcePciWdpeDetect: 1; // 56
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ULONG EnablePciNmi: 1; // 57
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ULONG EnablePciDti: 1; // 58
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ULONG EnablePciSerr: 1; // 59
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ULONG EnablePciPerr: 1; // 60
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ULONG EnablePciRdp: 1; // 61
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ULONG EnablePciAp: 1; // 62
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ULONG EnablePciWdp: 1; // 63
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};
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ULONGLONG all;
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} T2_IOCSR, *PT2_IOCSR;
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typedef union _T2_CERR1 {
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struct {
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ULONG UncorrectableReadError: 1; // 00
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ULONG NoAcknowledgeError: 1; // 01
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ULONG CommandAddressParityError: 1; // 02
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ULONG MissedCommandAddressParity: 1; // 03
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ULONG ResponderWriteDataParityError: 1; // 04
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ULONG MissedRspWriteDataParityError: 1; // 05
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ULONG ReadDataParityError: 1; // 06
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ULONG MissedReadDataParityError: 1; // 07
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ULONG CaParityErrorLw0: 1; // 08
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ULONG CaParityErrorLw2: 1; // 09
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ULONG DataParityErrorLw0: 1; // 10
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ULONG DataParityErrorLw2: 1; // 11
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ULONG DataParityErrorLw4: 1; // 12
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ULONG DataParityErrorLw6: 1; // 13
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ULONG Reserved1: 2; // 14-15
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ULONG CmdrWriteDataParityError: 1; // 16
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ULONG BusSynchronizationError: 1; // 17
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ULONG InvalidPfnError: 1; // 18
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ULONG Mbz0: 13; // 19-31
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ULONG Mbz1: 8; // 32-39
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ULONG CaParityErrorLw1: 1; // 40
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ULONG CaParityErrorLw3: 1; // 41
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ULONG DataParityErrorLw1: 1; // 42
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ULONG DataParityErrorLw3: 1; // 43
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ULONG DataParityErrorLw5: 1; // 44
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ULONG DataParityErrorLw7: 1; // 45
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ULONG Mbz2: 18; // 46-63
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};
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ULONGLONG all;
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} T2_CERR1, *PT2_CERR1;
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typedef ULONGLONG T2_CERR2;
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typedef ULONGLONG T2_CERR3;
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typedef union _T2_PERR1 {
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struct {
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ULONG WriteDataParityError: 1; // 00
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ULONG AddressParityError: 1; // 01
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ULONG ReadDataParityError: 1; // 02
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ULONG ParityError: 1; // 03
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ULONG SystemError: 1; // 04
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ULONG DeviceTimeoutError: 1; // 05
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ULONG NonMaskableInterrupt: 1; // 06
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ULONG PpcSizeError: 1; // 07 (T3/T4)
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ULONG WriteDataParityError64: 1; // 08 (T3/T4)
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ULONG AddressParityError64: 1; // 09 (T3/T4)
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ULONG ReadDataParityError64: 1; // 10 (T3/T4)
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ULONG TargetAbort: 1; // 11 (T3/T4)
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ULONG Mbz0: 4; // 12-15
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ULONG ForceReadDataParityError64: 1; // 16 (T3/T4)
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ULONG ForceAddressParityError64: 1; // 17 (T3/T4)
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ULONG ForceWriteDataParityError64: 1; // 18 (T3/T4)
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ULONG DetectTargetAbort: 1; // 19 (T3/T4)
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ULONG Reserved1: 12; // 20-31
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ULONG Reserved; // 32-63
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};
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ULONGLONG all;
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} T2_PERR1, *PT2_PERR1;
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typedef union _T2_PERR2 {
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struct {
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ULONG ErrorAddress; // 00
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ULONG PciCommand: 4; // 32
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ULONG Reserved: 28; // 36-63
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};
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ULONGLONG all;
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} T2_PERR2, *PT2_PERR2;
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typedef struct _T2_WBASE {
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union {
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struct {
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ULONG PciWindowEndAddress: 12; // 00
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ULONG Reserved0: 5; // 12
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ULONG EnablePeerToPeer: 1; // 17
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ULONG EnableScatterGather: 1; // 18
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ULONG EnablePciWindow: 1; // 19
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ULONG PciWindowStartAddress: 12; // 20
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ULONG Reserved; // 32-63
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};
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ULONGLONG all;
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};
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} T2_WBASE, *PT2_WBASE;
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typedef struct _T2_WMASK {
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union {
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struct {
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ULONG Reserved0: 20; // 00
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ULONG PciWindowMask: 11; // 20
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ULONG Reserved1: 1; // 31
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ULONG Reserved; // 32-63
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};
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ULONGLONG all;
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};
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} T2_WMASK, *PT2_WMASK;
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typedef struct _T2_TBASE {
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union {
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struct {
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ULONG Reserved0: 9; // 00
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ULONG TranslatedBaseAddress: 22; // 09
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ULONG Reserved1: 1; // 31
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ULONG Reserved; // 32-63
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};
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ULONGLONG all;
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};
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} T2_TBASE, *PT2_TBASE;
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typedef struct _T2_HBASE {
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union {
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struct {
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ULONG HoleEndAddress: 9; // 00
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ULONG Reserved1: 4; // 09
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ULONG Hole1Enable: 1; // 13
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ULONG Hole2Enable: 1; // 14
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ULONG HoleStartAddress: 9; // 15
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ULONG Reserved2: 8; // 24
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ULONG Reserved3; // 32-63
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};
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ULONGLONG all;
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};
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} T2_HBASE, *PT2_HBASE;
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typedef struct _T2_TDR {
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ULONG Tag: 30; // 00
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ULONG Reserved1: 2; // 30
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ULONG Valid: 1; // 32
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ULONG Pfn: 18; // 33
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ULONG Reserved2: 13; // 51
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} T2_TDR, *PT2_TDR;
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typedef union _T2_VAR { // T3/T4 Vector Address Register
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struct {
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ULONGLONG Vector: 6; // 00-05
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ULONGLONG Eisa: 1; // 06
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ULONGLONG PassiveRelease: 1; // 07
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ULONGLONG Reserved: 56; // 08-63
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};
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ULONGLONG all;
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} T2_VAR, *PT2_VAR;
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typedef union _T2_ICE { // T3/T4 ICIC Enable Register
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struct {
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ULONGLONG EisaFlushAddress: 24; // 00-23
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ULONGLONG IcEnable: 1; // 24
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ULONGLONG HalfSpeedEnable: 1; // 25
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ULONGLONG Reserved: 38; // 26-63
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};
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ULONGLONG all;
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} T2_ICE, *PT2_ICE;
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//
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// DMA Window Values.
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//
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// The T2 will be initialized to allow 2 DMA windows.
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// The first window will be for the use of of ISA devices and DMA slaves
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// and therefore must have logical addresses below 16MB.
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// The second window will be for bus masters (non-ISA) and so may be
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// above 16MB.
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//
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// The arrangement of the windows will be as follows:
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//
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// Window Logical Start Address Window Size
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// ------ --------------------- -----------
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// Isa 8MB 8MB
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// Master 16MB 16MB
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//
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#define ISA_DMA_WINDOW_BASE (__8MB)
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#define ISA_DMA_WINDOW_SIZE (__8MB)
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#define MASTER_DMA_WINDOW_BASE (__16MB)
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#define MASTER_DMA_WINDOW_SIZE (__16MB)
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//
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// Define the software control registers for a DMA window.
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//
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typedef struct _WINDOW_CONTROL_REGISTERS {
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PVOID WindowBase;
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ULONG WindowSize;
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PVOID TranslatedBaseRegister[2];
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PVOID WindowBaseRegister[2];
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PVOID WindowMaskRegister[2];
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PVOID WindowTbiaRegister[2];
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} WINDOW_CONTROL_REGISTERS, *PWINDOW_CONTROL_REGISTERS;
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//
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// Define types of windows.
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//
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typedef enum _T2_WINDOW_NUMBER {
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T2IsaWindow,
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T2MasterWindow
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} T2_WINDOW_NUMBER, *PT2_WINDOW_NUMBER;
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//
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// Define T2 Window Control routines.
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//
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VOID
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HalpT2InitializeSfwWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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T2_WINDOW_NUMBER WindowNumber
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);
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VOID
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HalpT2ProgramDmaWindow(
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PWINDOW_CONTROL_REGISTERS WindowRegisters,
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PVOID MapRegisterBase
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);
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VOID
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HalpT2InvalidateTLB(
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PWINDOW_CONTROL_REGISTERS WindowRegisters
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);
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VOID
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WRITE_T2_REGISTER(
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PVOID,
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ULONGLONG
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);
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ULONGLONG
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READ_T2_REGISTER(
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PVOID
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);
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//
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// VOID
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// INITIALIZE_ISA_DMA_CONTROL(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Initialize the DMA Control software window registers for the ISA
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_ISA_DMA_CONTROL( WR ) \
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HalpT2InitializeSfwWindow( (WR), T2IsaWindow );
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//
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// VOID
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// INITIALIZE_MASTER_DMA_CONTROL(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Initialize the DMA Control software window registers for the ISA
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_MASTER_DMA_CONTROL( WR ) \
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HalpT2InitializeSfwWindow( (WR), T2MasterWindow );
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//
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// VOID
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// INITIALIZE_DMA_WINDOW(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters,
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// PTRANSLATION_ENTRY MapRegisterBase
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// )
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//
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// Routine Description:
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//
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// Program the control windows so that DMA can be started to the
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// DMA window.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window register
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// control structure.
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//
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// MapRegisterBase - Supplies the logical address of the scatter/gather
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// array in system memory.
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//
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// Return Value:
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//
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// None.
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//
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#define INITIALIZE_DMA_WINDOW( WR, MRB ) \
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HalpT2ProgramDmaWindow( (WR), (MRB) );
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//
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// VOID
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// INVALIDATE_DMA_TRANSLATIONS(
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// PWINDOW_CONTROL_REGISTERS WindowRegisters
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// )
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//
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// Routine Description:
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//
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// Invalidate all of the cached translations for a DMA window.
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// This function does not need to do any action on the T2 chip
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// because the T2 snoops the bus and keeps the translations coherent
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// via hardware.
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//
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// Arguments:
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//
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// WindowRegisters - Supplies a pointer to the software window control
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// registers.
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//
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// Return Value:
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//
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// None.
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//
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#define INVALIDATE_DMA_TRANSLATIONS( WR )
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//
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// Define the format of a translation entry aka a scatter/gather entry
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// or map register.
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//
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typedef struct _TRANSLATION_ENTRY{
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ULONG Valid: 1;
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ULONG Pfn: 31;
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ULONG Reserved;
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} TRANSLATION_ENTRY, *PTRANSLATION_ENTRY;
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//
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// VOID
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// HAL_MAKE_VALID_TRANSLATION(
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// PTRANSLATION_ENTRY Entry,
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// ULONG PageFrameNumber
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// )
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//
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// Routine Description:
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//
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// Make the scatter/gather entry pointed to by Entry valid with
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// a translation to the page indicated by PageFrameNumber.
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//
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// Arguments:
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//
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// Entry - Supplies a pointer to the translation entry to make valid.
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//
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// PageFrameNumber - Supplies the page frame of the valid translation.
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//
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// Return Value:
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//
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// None.
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//
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#define HAL_MAKE_VALID_TRANSLATION( ENTRY, PFN ) \
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{ \
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(ENTRY)->Valid = 1; \
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(ENTRY)->Pfn = PFN; \
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(ENTRY)->Reserved = 0; \
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}
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//
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||
// VOID
|
||
// HAL_INVALIDATE_TRANSLATION(
|
||
// PTRANSLATION_ENTRY Entry
|
||
// )
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// Invalidate the translation indicated by Entry.
|
||
//
|
||
// Arguments:
|
||
//
|
||
// Entry - Supplies a pointer to the translation to be invalidated.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
|
||
#define HAL_INVALIDATE_TRANSLATION( ENTRY ) \
|
||
(ENTRY)->Valid = 0;
|
||
|
||
#endif // T2H
|