278 lines
8.5 KiB
PHP
278 lines
8.5 KiB
PHP
;++
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;
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; Copyright (c) 1992, 1993, 1994 Corollary Inc
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;
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; Module Name:
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;
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; cbus.inc
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;
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; Abstract:
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;
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; Corollary MP include file
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;
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; Author:
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;
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; Landy Wang (landy@corollary.com) 26-Mar-1992
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;--
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;*****************************
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;
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; Corollary MP defines
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;
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; this should be built from a C header file to minimize
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; the possiblity of falling out of sync.
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;
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;*****************************
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;
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; Well known virtual address of the task priority register
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;
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LOCALAPIC equ 0fffe0000h
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APIC equ ds:[LOCALAPIC]
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;
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; The SPURIOUS task priority varies depending on Cbus platform.
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; It is set when we initialize the platform and cannot be declared
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; here. APC and DPC vectors are the same for Cbus1 and Cbus2
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; so they can be inlined here.
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;
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APC_TASKPRI equ 01Fh ; Hardware priority of APCs
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DPC_TASKPRI equ 02Fh ; Hardware priority of DPCs
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CBUS2_LEVEL_TRIGGERED_INTERRUPT equ 1
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CBUS2_EDGE_TRIGGERED_INTERRUPT equ 2
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;
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; Here is the assembly version of the CBUS_NTHAL structure declared in cbus_nt.h
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;
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RequestIPI equ 000h
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HalRequestSWIntr equ 004h
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HalQueryPerformanceCounter equ 008h
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HalBootCPU equ 00ch
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HalInitializePlatform equ 010h
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HalInitializeCPU equ 014h
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EnableNonDeviceInterrupt equ 018h
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EnableDeviceInterrupt equ 01ch
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DisableInterrupt equ 020h
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LinkInterrupt equ 024h
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MapVector equ 028h
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ParseRRD equ 02ch
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ResolveNMI equ 030h
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HalInitInterrupts equ 034h
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HalResetAllOtherProcessors equ 038h
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HalInitOtherBuses equ 03ch
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HalSetTimeIncrement equ 040h
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HalTranslateAddress equ 044h
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;
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; The kernel leaves some space in the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation
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; dependent. this order MUST match the definitions in cbus_nt.h.
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;
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PcrE struc
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PcrNumber dd 0 ; this CPU's logical CPU number
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PcrBit dd 0 ; this CPU's logical bit number
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PcrCSR dd 0 ; pointer to this CPU's CSR
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PcrTaskpri dd 0 ; taskpri reg ptr
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PcrBroadcast dd 0 ; interrupt everyone but this CPU
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PcrAllOthers dd 0 ; all other CPUs but this one
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PcrLEDOn dd 0 ; pointer to this CPU's LED ON
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PcrLEDOff dd 0 ; pointer to this CPU's LED OFF
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PcrTickOffset dd 0 ; nsec left before calling
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; KeUpdateRunTime on CPU1 or above
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PcrE ends
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;
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; Offsets of various registers needed for the context switch when
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; a system reboot is initiated by an additional processor.
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; the space for this array is declared in cbus.c - so bump it there
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; if you need more...
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;
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REBOOT_EIP equ 0
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REBOOT_ESP equ 4
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REBOOT_EBP equ 8
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REBOOT_EBX equ 12
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REBOOT_ESI equ 16
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REBOOT_EDI equ 20
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REBOOT_EFL equ 24
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REBOOT_CR3 equ 28
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;
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; ack the interrupt controller (CBC or APIC).
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;
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; we must derive the bus number so we know which bus' interrupt
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; controller to EOI for systems with multiple I/O busses.
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; so translate the vector to a bus/irqline pair for the EOI...
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;
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; WARNING: for the APIC, this will automatically lower the
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; internal priority register to the level it was prior to
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; receipt of the interrupt.
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;
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; the caller must initialize scratchreg to the interrupting vector.
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;
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CBUS_EOI macro reg1, reg2
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local fix_level
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local check_cpu
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local do_eoi
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local no_eoi
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;
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; reg1 holds the vector that originally interrupted execution,
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; now translate the vector to the correct bridge-based EOI address.
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;
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cmp reg1, [_Cbus2ClockVector]
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je short check_cpu
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cmp [_Cbus2FixLevelInterrupts], 1
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jne short do_eoi
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;
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; first check the polarity of the interrupt (ie. level or edge)
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; to determine whether the level-triggered interrupt hardware
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; work-around need be applied. need to ensure that no interrupts
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; occur while we're performing the workaround for the level-triggered
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; interrupt fix. the fix consists of clearing and resetting the
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; hardware interrupt map entry for this vector. this will cause
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; an internal latch in the CBC to be cleared. this problem will
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; be fixed with the PCIB, at which time, RRD will pass a bit in
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; the configuration table which will cause this code to no longer
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; be executed.
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;
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fix_level:
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movzx reg2, byte ptr [_Cbus2InterruptPolarity + reg1]
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cmp reg2, CBUS2_LEVEL_TRIGGERED_INTERRUPT
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jne short do_eoi
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mov reg2, dword ptr [_CbusVectorToEoi+4*reg1]
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sub reg2, [_Cbus2EoiToHwmap]
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mov reg1, dword ptr [_CbusVectorToHwmap+4*reg1]
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pushfd
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cli
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mov dword ptr [reg2], 0
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mov dword ptr [reg2], reg1 ; must _write_ EOI
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popfd
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jmp short no_eoi
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check_cpu:
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;
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; on C-bus II, the clock interrupt must only be EOI'd by
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; a single CPU. make it the boot CPU so that this code
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; will work when only 1 CPU is present.
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;
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cmp dword ptr PCR[PcHal.PcrNumber], 0
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jne short no_eoi
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cmp [_Cbus2FixLevelInterrupts], 1
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je short fix_level
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do_eoi:
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mov reg2, dword ptr [_CbusVectorToEoi+4*reg1]
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mov dword ptr dword ptr [reg2], reg1 ; must _write_ EOI
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no_eoi:
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endm
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POKE_LEDS macro reg1, reg2
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local ledset
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mov reg1, PCR[PcPrcb] ; point at Prcb
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mov reg2, [reg1].PbCurrentThread ; Current thread
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cmp reg2, [reg1].PbIdleThread ; Idle Thread
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je short @f
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mov reg1, PCR[PcHal.PcrLEDOn] ; get my LED ON address
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mov dword ptr [reg1], 1 ; set it
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jmp short ledset
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@@:
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mov reg1, PCR[PcHal.PcrLEDOff] ; get my LED OFF address
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mov dword ptr [reg1], 0 ; set it
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ledset:
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endm
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;
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; Declare all the externs that most of our MASM code will be using
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;
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extrn _CbusLocalApic: DWORD
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extrn _CbusApicRedirPort: DWORD
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extrn _CbusIOApic: DWORD
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extrn _ProfileVector: DWORD
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;
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; vectors used to communicate reboot and redirection table requested
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; changes to the boot processor. also the global interprocessor ; interrupt vector that any processor can use to interrupt any other
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; processor(s).
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;
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extrn _CbusIpiVector: DWORD
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extrn _CbusRebootVector: DWORD
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extrn _CbusRedirVector: DWORD
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extrn _CbusClockVector: DWORD
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extrn _CbusQueryPerformanceCounter: DWORD
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extrn _CbusVectorToIrql: DWORD
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extrn _CbusIrqlToVector: DWORD
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extrn _CbusBackend: DWORD
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extrn _CbusRequestIPI: DWORD
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extrn _CbusRequestSoftwareInterrupt: DWORD
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extrn _CbusProcessorMask: DWORD
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extrn _CbusBootedProcessors: DWORD
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extrn _CbusRebootRegs: DWORD
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extrn _Cbus2BridgesFound: DWORD
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extrn _Cbus2SendIPI: DWORD
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extrn _Cbus2Poke8042: DWORD
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extrn _Cbus2IrqlToCbus2Addr: DWORD
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extrn _Cbus2FixLevelInterrupts: DWORD
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extrn _Cbus2CheckSpuriousClock: DWORD
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extrn _Cbus2EnableBroadcast: DWORD
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extrn _Cbus2ClockVector: DWORD
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extrn _Cbus2InterruptPolarity: DWORD
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extrn _Cbus2EoiToHwmap: DWORD
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extrn _CbusTimeStamp: DWORD
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extrn _Cbus2TimeStamp0: DWORD
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extrn _CbusVectorToEoi: DWORD
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extrn _CbusVectorToHwmap: DWORD
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extrn _CbusProcessors: DWORD
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extrn _HalpFindFirstSetRight: BYTE
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extrn _Halp8254Lock: DWORD
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extrn _MppIDT: DWORD
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extrn _MpLowStub: DWORD
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extrn _MpLowStubPhysicalAddress: DWORD
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extrn _MpCount: DWORD
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;
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; Declare all the functions that our MASM code will be calling
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;
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EXTRNP _DbgBreakPoint,0,IMPORT
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EXTRNP _HalEnableSystemInterrupt, 3
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EXTRNP _HalDisableSystemInterrupt, 2
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EXTRNP _HalpAcquireCmosSpinLock, 0
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EXTRNP _HalpReleaseCmosSpinLock, 0
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EXTRNP _KeBugCheck,1,IMPORT
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EXTRNP _KeSetTimeIncrement,2,IMPORT
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EXTRNP _KeUpdateRunTime,1,IMPORT
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EXTRNP _KeUpdateSystemTime,0
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EXTRNP Kei386EoiHelper,0,IMPORT
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EXTRNP _KiIpiServiceRoutine,2,IMPORT
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EXTRNP _KiDeliverApc,3,IMPORT
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EXTRNP _KiDispatchInterrupt,0,IMPORT
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EXTRNP _ExAllocatePool,2,IMPORT
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EXTRNP _HalpBuildTiledCR3,1
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EXTRNP _HalpFreeTiledCR3,0
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EXTRNP _HalpProfileInterrupt2ndEntry,0
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