71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/*++
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Copyright (c) 1992, 1993, 1994 Corollary Inc.
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Module Name:
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cbus1.h
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Abstract:
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Cbus1 architecture definitions for the Corollary Cbus1
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multiprocessor HAL modules.
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Author:
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Landy Wang (landy@corollary.com) 05-Oct-1992
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#ifndef _CBUS1_
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#define _CBUS1_
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//
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//
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// FIRST, THE CBUS1 HARDWARE ARCHITECTURE DEFINITIONS
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//
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//
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#define COUTB(addr, reg, val) (((PUCHAR)(addr))[reg] = (UCHAR)val)
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#define CBUS1_CACHE_LINE 16 // 16 byte lines
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#define CBUS1_CACHE_SHIFT 4 // byte size to line size
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#define CBUS1_CACHE_SIZE 0x100000 // 1 Mb caches
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#define ATB_STATREG (PUCHAR)0xf1 // EISA bridge status register
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#define BS_ARBVALUE 0xf // arbitration value
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#define LOWCPUID 0x1 // lowest arbitration slot id
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#define HICPUID 0xf // highest arbitration slot id
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#define CBUS1_SHADOW_REGISTER 0xB0 // offset of shadow register
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#define DISABLE_BIOS_SHADOWING 0x0 // disable ROM BIOS shadowing
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//
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// defines for the Cbus1 ecc control register
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//
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#define CBUS1_EDAC_SAEN 0x80
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#define CBUS1_EDAC_1MB 0x40
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#define CBUS1_EDAC_WDIS 0x20
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#define CBUS1_EDAC_EN 0x10
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#define CBUS1_EDAC_SAMASK 0xf
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//
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// Physical address of the Cbus1 local APIC
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//
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#define CBUS1_LOCAL_APIC_LOCATION (PVOID)0xFEE00000
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//
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// Physical address of the Cbus1 I/O APIC
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//
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#define CBUS1_IO_APIC_LOCATION (PVOID)0xFEE00000
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#endif // _CBUS1_
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