398 lines
11 KiB
C
398 lines
11 KiB
C
/*++
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Copyright (c) 1992, 1993, 1994 Corollary Inc.
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Module Name:
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cbus2.h
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Abstract:
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Cbus2 hardware architecture definitions for the
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Corollary C-bus II multiprocessor HAL modules.
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Author:
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Landy Wang (landy@corollary.com) 26-Mar-1992
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#ifndef _CBUS2_
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#define _CBUS2_
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//
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// General notes:
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//
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// - ALL reserved fields must be zero filled on writes to
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// ensure future compatibility.
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//
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// - general CSR register length is 64 bits.
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//
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//
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typedef struct _csr_register_t {
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ULONG LowDword; // 32 bit field
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ULONG HighDword; // 32 bit field
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} CSR_REGISTER_T, *PCSR_REG;
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typedef union _elementid_t {
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struct {
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ULONG ElementID : 4;
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ULONG Reserved0 : 28;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} ELEMENTID_T, *PELEMENTID;
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typedef union _spurious_t {
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struct {
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ULONG Vector : 8;
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ULONG Reserved0 : 24;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} SPURIOUS_T;
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typedef union _windowreloc_t {
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struct {
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ULONG WindowBase : 9;
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ULONG Reserved0 : 23;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} WINDOWRELOC_T;
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//
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// The hardware interrupt map table (16 entries) is indexed by irq.
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// Lower numerical irq lines will receive higher interrupt (IRQL) priority.
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//
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// Each CBC has its own hardware interrupt map registers . note that
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// each processor gets his own CBC, but it need only be used in this
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// mode if there is an I/O card attached to its CBC. each EISA bridge
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// will have a CBC, which is used to access any devices on that EISA bus.
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//
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typedef union _hwintrmap_t {
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struct {
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ULONG Vector : 8;
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ULONG Mode : 3;
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ULONG Reserved0 : 21;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} HWINTRMAP_T, *PHWINTRMAP;
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/*
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* interrupt trigger conditions
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*/
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#define HW_MODE_DISABLED 0x0
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#define HW_EDGE_RISING 0x100 /* ie: ISA card interrupts */
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#define HW_EDGE_FALLING 0x200
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#define HW_LEVEL_HIGH 0x500
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#define HW_LEVEL_LOW 0x600
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/*
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* CBC rev 1 value for the number of hardware interrupt map entries
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*/
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#define REV1_HWINTR_MAP_ENTRIES 0x10
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/*
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* max growth for the number of hardware interrupt map entries
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*/
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#define HWINTR_MAP_ENTRIES 0x20
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//
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// 256 intrconfig registers for vectors 0 to 255. this determines how
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// a given processor will react to each of these vectors. each processor
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// has his own intrconfig table in his element space.
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//
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typedef union _intrconfig_t {
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struct {
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ULONG Imode : 2;
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ULONG Reserved0 : 30;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} INTRCONFIG_T, *PINTRCONFIG;
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#define HW_IMODE_DISABLED 0x0
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#define HW_IMODE_ALLINGROUP 0x1
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#define HW_IMODE_LIG 0x2
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#define INTR_CONFIG_ENTRIES 0x100
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#define CBUS2_LEVEL_TRIGGERED_INTERRUPT 1
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#define CBUS2_EDGE_TRIGGERED_INTERRUPT 2
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//
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// 256 interrupt request registers for vectors 0 to 255.
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// parallel to the interrupt config register set above.
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// This is used to send the corresponding interrupt vector.
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// which processor gets it is determined by which element's
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// address space you write to.
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//
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// The irq field should always be set when accessed by software.
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// only hardware LIG arbitration will clear it.
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//
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typedef union _intrreq_t {
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struct {
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ULONG Irq : 1;
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ULONG Reserved0 : 31;
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ULONG Reserved1 : 32;
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} ra;
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CSR_REGISTER_T rb;
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} INTRREQ_T, *PINTRREQ;
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//
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// the Cbus2 task priority register bit layout and
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// minimum/maximum values are defined in cbus.h, as
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// they need to be shared with the symmetric Cbus1.
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//
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//
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// bit 7 of the CBC configuration register must be turned off to enable
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// posted writes for EISA I/O cycles.
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//
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#define CBC_DISABLE_PW 0x80
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//
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// Offsets of various registers within the processor CSR space.
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//
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typedef struct _csr {
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CSR_REGISTER_T ElementTypeInformation; // 0x0000
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CSR_REGISTER_T IoTypeInformation; // 0x0008
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CSR_REGISTER_T ProcessorReset; // 0x0010
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CSR_REGISTER_T DirectedNmi; // 0x0018
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CSR_REGISTER_T LED; // 0x0020
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CHAR pad0[0x90 - 0x20 - sizeof (CSR_REGISTER_T)];
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CSR_REGISTER_T PcBusMemoryHoles0; // 0x0090
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CSR_REGISTER_T PcBusMemoryHoles1; // 0x0098
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CSR_REGISTER_T PcBusMemoryHoles2; // 0x00A0
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CSR_REGISTER_T TLM; // 0x00A8
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CHAR pad00[0x100 - 0xA8 - sizeof (CSR_REGISTER_T)];
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ELEMENTID_T BusBridgeSelection; // 0x0100
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WINDOWRELOC_T BridgeWindow0; // 0x0108
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WINDOWRELOC_T BridgeWindow1; // 0x0110
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CHAR pad1[0x200 - 0x110 - sizeof (WINDOWRELOC_T)];
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TASKPRI_T TaskPriority; // 0x0200
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CSR_REGISTER_T pad2; // 0x208
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CSR_REGISTER_T FaultControl; // 0x210
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CSR_REGISTER_T FaultIndication; // 0x218
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CSR_REGISTER_T InterruptControl; // 0x220
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CSR_REGISTER_T ErrorVector; // 0x228
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CSR_REGISTER_T InterruptIndication; // 0x230
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CSR_REGISTER_T PendingPriority; // 0x238
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SPURIOUS_T SpuriousVector; // 0x0240
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CHAR pad3[0x600 - 0x240 - sizeof (CSR_REGISTER_T)];
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HWINTRMAP_T HardwareInterruptMap[HWINTR_MAP_ENTRIES]; // 0x0600
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CSR_REGISTER_T HardwareInterruptMapEoi[HWINTR_MAP_ENTRIES]; // 0x0700
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INTRCONFIG_T InterruptConfiguration[INTR_CONFIG_ENTRIES]; // 0x0800
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INTRREQ_T InterruptRequest[INTR_CONFIG_ENTRIES]; // 0x1000
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CHAR pad4[0x2000 - 0x1000 -
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INTR_CONFIG_ENTRIES * sizeof (INTRREQ_T)];
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CSR_REGISTER_T SystemTimer; // 0x2000
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CHAR pad5[0x2140 - 0x2000 - sizeof(CSR_REGISTER_T)];
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CSR_REGISTER_T EccError; // 0x2140
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CHAR pad6[0x3000 - 0x2140 - sizeof(CSR_REGISTER_T)];
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CSR_REGISTER_T EccClear; // 0x3000
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CSR_REGISTER_T EccSyndrome; // 0x3008
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CSR_REGISTER_T EccWriteAddress; // 0x3010
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CSR_REGISTER_T EccReadAddress; // 0x3018
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CHAR pad7[0x8000 - 0x3018 - sizeof(CSR_REGISTER_T)];
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CSR_REGISTER_T CbcConfiguration; // 0x8000
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} CSR_T, *PCSR;
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//
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// Offsets of various registers within the memory board CSR space.
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//
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typedef struct _memcsr {
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CHAR pad0[0x10];
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CSR_REGISTER_T MemoryFaultStatus; // 0x0010
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CHAR pad1[0x3020 - 0x10 - sizeof (CSR_REGISTER_T)];
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CSR_REGISTER_T MemoryEccReadAddress; // 0x3020
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CSR_REGISTER_T MemoryEccWriteAddress; // 0x3028
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CSR_REGISTER_T MemoryEccClear; // 0x3028
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CSR_REGISTER_T MemoryEccSyndrome; // 0x3030
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} MEMCSR_T, *PMEMCSR;
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//
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// Interrupt Indication register bit that a fault occurred. This applies
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// to the processor CSR.
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//
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#define CBUS2_FAULT_DETECTED 0x2
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//
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// Fault Indication register bits for errors this processor's CSR has latched.
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//
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#define CBUS2_BUS_DATA_UNCORRECTABLE 0x2
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#define CBUS2_BUS_ADDRESS_UNCORRECTABLE 0x10
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//
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// Fault Status register bit for errors latched by this memory board's CSR.
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//
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#define CBUS2_MEMORY_FAULT_DETECTED 0x80
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//
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// RRD will provide an entry for every Cbus2 element. To avoid
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// using an exorbitant number of PTEs, this entry will specify
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// only the CSR space within each Cbus2 element's space. And only
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// a subset of that, as well, usually on the order of 4 pages.
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// Code wishing to access other portions of the cbus_element
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// space will need to subtract down from the RRD-specified CSR
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// address and map according to their particular needs.
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//
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#define MAX_CSR_BYTES 0x10000
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#define csr_register rb.LowDword
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//
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// The full layout of a cbus2 element space:
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//
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// Note that only the Csr offset/size is passed up by RRD, and
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// mapped by the HAL. before referencing any other fields, the
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// caller must first set up appropriate PDE/PTE entries.
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//
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typedef struct _cbus2element {
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CHAR PCBusRAM [16 * 1024 * 1024];
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CHAR PCBusWindow0 [8 * 1024 * 1024];
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CHAR PCBusWindow1 [8 * 1024 * 1024];
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CHAR DeviceReserved [28 * 1024 * 1024];
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CHAR ControlIO [0x10000];
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CHAR PCBusIO [0x10000];
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CHAR Csr [MAX_CSR_BYTES];
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CHAR IdentityMappedCsr [MAX_CSR_BYTES];
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CHAR Reserved [0x1C0000];
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CHAR Ram [0x100000];
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CHAR Prom [0x100000];
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} CBUS2_ELEMENT, *PCBUS2_ELEMENT;
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//
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// offset of CSR within any element's I/O space.
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//
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#define CBUS_CSR_OFFSET 0x3C20000
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//
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// id of the default C-bus II bridge
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//
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#define CBUS2_DEFAULT_BRIDGE_ID 0
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//
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// reserved element types
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//
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#define CBUS2_ELEMENT_TYPE_RAS 0x50
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//
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// Shift for PC Bus Window CSRs
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//
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#define CBUS2_WINDOW_REGISTER_SHIFT 23
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//
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// PC Bus memory hole defines to designate all memory
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// holes go to system memory.
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//
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#define CBUS2_NO_MEMORY_HOLES 0x3f;
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#define CBUS2_NO_MEMORY_HOLES1 0xff;
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#define CBUS2_NO_MEMORY_HOLES2 0xffff;
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//
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// turn the LED on or off.
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//
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#define CBUS2_LED_OFF 0
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#define CBUS2_LED_ON 1
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//
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//
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// Physical address of the Cbus2 local APIC
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//
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#define CBUS2_LOCAL_APIC_LOCATION (PVOID)0xFEE00000
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//
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// Physical address of the Cbus2 I/O APIC
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//
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#define CBUS2_IO_APIC_LOCATION (PVOID)0xFEC00000
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//
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// Programmed I/O translation ranges
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//
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#define CBUS2_IO_BASE_ADDRESS 0x0000
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#define CBUS2_IO_LIMIT 0xFFFF
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//
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// PCI macros used to fill in the configuration space of a PPB
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//
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#define PCI_IO_TO_CFG(x) ((UCHAR)(((x) & 0xF000) >> 8))
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#define PCI_MEMORY_TO_CFG(x) ((USHORT)(((x) & 0xFFF00000) >> 16))
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#define PCI_PREFETCH_TO_CFG(x) ((USHORT)(((x) & 0xFFF00000) >> 16))
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#define CBUS2_PCI_LATENCY_TIMER 0x60
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typedef struct _cbus2_host_bridge_config {
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USHORT VendorID; // (ro) 0x0000
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USHORT DeviceID; // (ro) 0x0002
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USHORT Command; // Device control 0x0004
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USHORT Status; // 0x0006
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UCHAR RevisionID; // (ro) 0x0008
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UCHAR ProgIf; // (ro) 0x0009
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UCHAR SubClass; // (ro) 0x000A
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UCHAR BaseClass; // (ro) 0x000B
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UCHAR CacheLineSize; // (ro+) 0x000C
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UCHAR LatencyTimer; // (ro+) 0x000D
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UCHAR HeaderType; // (ro) 0x000E
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UCHAR BIST; // Built in self test 0x000F
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UCHAR pad1[0x4A - 0XF - sizeof (UCHAR)];
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UCHAR BusNumber; // 0x004A
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UCHAR SubordinateBusNumber; // 0x004B
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UCHAR pad2[0x70 - 0X4B - sizeof (UCHAR)];
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UCHAR ErrorCommand; // 0x0070
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UCHAR ErrorStatus; // 0x0071
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UCHAR MasterCommand; // 0x0072
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UCHAR pad3;
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UCHAR DiagnosticMode; // 0x0074
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UCHAR pad4[0xFF - 0x74 - sizeof (UCHAR)];
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} CBUS2_HOST_BRIDGE_CONFIG, *PCBUS2_HOST_BRIDGE_CONFIG;
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#endif // _CBUS2_
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