68 lines
1.3 KiB
ArmAsm
68 lines
1.3 KiB
ArmAsm
//++
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//
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// Copyright (c) 1993-1995 IBM Corporation
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//
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// Copyright (c) 1994, 1995 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// pxpower.s
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//
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// Abstract:
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//
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// This module implements the routines to flush cache on the PowerPC.
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//
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// Author:
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//
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// Steve Johns - Motorola
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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// 12-Sep-94 saj Wrote it
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// 25-Oct-94 saj Enable interrupts if 604
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// Set DOZE bit in HID0 before POW in MSR
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// 25-Sep-95 kjr Added 603ev support.
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//--
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#include "kxppc.h"
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.set HID0, 1008 // SPR # for HID0
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LEAF_ENTRY(HalpProcessorIdle)
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mfmsr r.4 // Read MSR
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ori r.4, r.4, 0x8000 // Enable External/Decrementer interrupts
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mfpvr r.0 // Read PVR
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rlwinm r.0, r.0, 16, 15, 31
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cmpwi r.0, 3 // Is it a 603?
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beq EnableDoze
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cmpwi r.0, 6 // Is it a 603e?
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beq EnableDoze
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cmpwi r.0, 7 // Is it a 603ev?
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beq EnableDoze
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b EnableInterrupts // If not, just enable interrupts
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EnableDoze:
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mfspr r.3, HID0 // Set Doze mode in HID0 (bit 8)
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oris r.3, r.3, 0x0080
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mtspr HID0, r.3
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sync
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oris r.4, r.4, 0x0004 // Set POW in MSR (bit 13)
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EnableInterrupts:
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mtmsr r.4
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isync
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LEAF_EXIT(HalpProcessorIdle)
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