613 lines
12 KiB
C
613 lines
12 KiB
C
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1992, 1993 Digital Equipment Corporation
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Module Name:
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ebintsup.c
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Abstract:
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The module provides the interrupt support for EB66/Mustang systems.
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Author:
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Eric Rehm (DEC) 29-December-1993
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Revision History:
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Dick Bissen [DEC] 12-May-1994
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Removed all support of the EB66 pass1 module from the code.
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--*/
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#include "halp.h"
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#include "eisa.h"
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#include "ebsgdma.h"
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#include "eb66def.h"
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#include "pcrtc.h"
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#include "pintolin.h"
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//
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// Global to control interrupt handling for EB64+
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//
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UCHAR IntMask0, IntMask1, IntMask2;
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VOID
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HalpInitializePciInterrupts (
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VOID
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);
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BOOLEAN
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HalpPCIDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PKTRAP_FRAME TrapFrame
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);
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//
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// Define the context structure for use by interrupt service routines.
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//
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typedef BOOLEAN (*PSECOND_LEVEL_DISPATCH)(
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PKINTERRUPT InterruptObject
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);
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//
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// The following is the interrupt object used for DMA controller interrupts.
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// DMA controller interrupts occur when a memory parity error occurs or a
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// programming error occurs to the DMA controller.
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//
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KINTERRUPT HalpEisaNmiInterrupt;
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//
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// The following function initializes NMI handling.
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//
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VOID
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HalpInitializeNMI(
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VOID
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);
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//
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// The following functions is called when an EISA NMI occurs.
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//
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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);
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VOID
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HalpDisableSioInterrupt(
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IN ULONG Vector
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);
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VOID
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HalpEnableSioInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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);
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BOOLEAN
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HalpInitializePCIInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the structures necessary for EISA & PCI operations
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and connects the intermediate interrupt dispatcher. It also initializes the
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EISA interrupt controller.
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Arguments:
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None.
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Return Value:
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If the second level interrupt dispatcher is connected, then a value of
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TRUE is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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UCHAR DataByte;
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KIRQL oldIrql;
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UCHAR *SystemType;
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//
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// Initialize the SIO NMI interrupt.
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//
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HalpInitializeNMI();
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//
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// Directly connect the ISA interrupt dispatcher to the level for
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// ISA bus interrupt.
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//
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// N.B. This vector is reserved for exclusive use by the HAL (see
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// interrupt initialization.
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//
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PCR->InterruptRoutine[PIC_VECTOR] = (PVOID)HalpPCIDispatch;
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HalEnableSystemInterrupt(PIC_VECTOR, DEVICE_LEVEL, LevelSensitive);
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if (SystemIsEB66P)
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(PVOID) HalpPCIPinToLineTable = (PVOID) EB66PPCIPinToLineTable;
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else
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(PVOID) HalpPCIPinToLineTable = (PVOID) EB66PCIPinToLineTable;
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//
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// Raise the IRQL while the PCI interrupt controller is initalized.
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//
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KeRaiseIrql(PCI_DEVICE_LEVEL, &oldIrql);
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//
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// Initialize the PCI interrupts.
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//
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HalpInitializePciInterrupts();
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//
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// Initialize SIO Programmable Interrupt Contoller
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//
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HalpInitializeSioInterrupts();
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//
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// Restore IRQL level.
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//
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KeLowerIrql(oldIrql);
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//
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// Initialize the DMA mode registers to a default value.
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// Disable all of the DMA channels except channel 4 which is the
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// cascade of channels 0-3.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
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0x0F
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
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0x0E
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);
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return(TRUE);
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}
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BOOLEAN
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HalpPCIDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PKTRAP_FRAME TrapFrame
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)
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/*++
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Routine Description:
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This routine is entered as the result of an interrupt being generated
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via the vector that is connected to an interrupt object that describes
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the PCI and ISA device interrupts. Its function is to call the second
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level interrupt dispatch routine and acknowledge the interrupt at the ISA
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controller.
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This service routine should be connected as follows:
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KeInitializeInterrupt(&Interrupt, HalpPCIDispatch,
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EISA_VIRTUAL_BASE,
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(PKSPIN_LOCK)NULL, PCI_LEVEL, PCI_LEVEL, PCI_LEVEL,
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LevelSensitive, TRUE, 0, FALSE);
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KeConnectInterrupt(&Interrupt);
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object.
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ServiceContext - Supplies a pointer to the ISA interrupt acknowledge
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register.
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TrapFrame - Supplies a pointer to the trap frame for this interrupt.
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Return Value:
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Returns the value returned from the second level routine.
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--*/
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{
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UCHAR PciVector, IntNumber;
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ULONG PCRInOffset = 0xffff;
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KPCR *pcr;
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//
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// Read in the 1st interrupt register.
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//
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PciVector = READ_PORT_UCHAR(INTERRUPT_MASK0_QVA) & IntMask0;
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//
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// Was it an ISA (SIO) interrupt?
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//
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if (PciVector & SIO_INTERRUPT_MASK) {
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//
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// ISA interrupt - call HalpSioDispatch().
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//
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return HalpSioDispatch();
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}
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//
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// Which PCI interrupt was it?
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//
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if (PciVector) {
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for(IntNumber = 0; IntNumber < 8; IntNumber++) {
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if (PciVector & 1) {
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PCRInOffset = IntNumber;
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break;
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}
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PciVector >>= 1;
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}
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} else {
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PciVector = READ_PORT_UCHAR(INTERRUPT_MASK1_QVA) & IntMask1;
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if (PciVector) {
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for(IntNumber = 0; IntNumber < 8; IntNumber++) {
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if (PciVector & 1) {
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PCRInOffset = IntNumber + 8;
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break;
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}
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PciVector >>= 1;
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}
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} else if (INTERRUPT_MASK2_QVA != NULL) {
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PciVector = READ_PORT_UCHAR(INTERRUPT_MASK2_QVA) & IntMask2;
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if (PciVector)
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PCRInOffset = 0x10;
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}
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}
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if (PCRInOffset == 0xffff) {
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return FALSE;
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}
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PCRInOffset += PCI_VECTORS;
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PCRInOffset++;
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return ((PSECONDARY_DISPATCH)PCR->InterruptRoutine[PCRInOffset])(
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PCR->InterruptRoutine[PCRInOffset], TrapFrame);
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}
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VOID
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HalpDisablePCIInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function Disables the PCI bus specified PCI bus interrupt.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is Disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector.
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//
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Vector -= PCI_VECTORS;
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Vector--;
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//
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// Clear the corresponding bit in the appropriate interrupt mask
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// shadow and write it out to the interrupt mask.
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//
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if (Vector >= 0 && Vector <= 7) {
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IntMask0 &= (UCHAR) ~(1 << Vector);
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WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
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} else if (Vector >= 8 && Vector <= 0xf) {
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IntMask1 &= (UCHAR) ~(1 << (Vector - 8));
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WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
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} else if ((Vector == 0x10) && (INTERRUPT_MASK2_QVA != NULL)) {
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IntMask2 = 0;
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WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
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} else {
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#ifdef HALDBG
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DbgPrint("HalpDisablePCIInterrupt: bad vector\n");
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#endif // HALDBG
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}
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}
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VOID
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HalpEnablePCIInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function enables the PCI bus specified PCI bus interrupt.
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PCI interrupts must be LevelSensitve. (PCI Spec. 2.2.6)
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Arguments:
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Vector - Supplies the vector of the ESIA interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector.
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//
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Vector -= PCI_VECTORS;
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Vector--;
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//
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// Set the corresponding bit in the appropriate interrupt mask
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// shadow and write it out to the interrupt mask.
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//
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if (Vector >= 0 && Vector <= 7) {
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IntMask0 |= (UCHAR) (1 << Vector);
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WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
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} else if (Vector >= 8 && Vector <= 0xf) {
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IntMask1 |= (UCHAR) (1 << (Vector - 8));
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WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
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} else if ((Vector == 0x10) && (INTERRUPT_MASK2_QVA != NULL)) {
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IntMask2 = 1;
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WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
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} else {
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#ifdef HALDBG
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DbgPrint("HalpEnablePCIInterrupt: bad vector\n");
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#endif // HALDBG
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}
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}
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VOID
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HalpInitializeNMI(
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VOID
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)
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/*++
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Routine Description:
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This function is called to intialize SIO NMI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR DataByte;
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//
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// Initialize the SIO NMI interrupt.
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//
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KeInitializeInterrupt( &HalpEisaNmiInterrupt,
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HalHandleNMI,
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NULL,
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NULL,
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EISA_NMI_VECTOR,
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EISA_NMI_LEVEL,
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EISA_NMI_LEVEL,
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LevelSensitive,
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FALSE,
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0,
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FALSE
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);
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//
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// Don't fail if the interrupt cannot be connected.
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//
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KeConnectInterrupt( &HalpEisaNmiInterrupt );
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//
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// Clear the Eisa NMI disable bit. This bit is the high order of the
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// NMI enable register.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
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DataByte
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);
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}
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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)
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/*++
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Routine Description:
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This function is called when an EISA NMI occurs. It print the appropriate
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status information and bugchecks.
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object
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ServiceContext - Bug number to call bugcheck with.
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Return Value:
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Returns TRUE.
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--*/
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{
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UCHAR StatusByte;
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UCHAR EisaPort;
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ULONG port;
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ULONG AddressSpace = 1; // 1 = I/O address space
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BOOLEAN Status;
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PHYSICAL_ADDRESS BusAddress;
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PHYSICAL_ADDRESS TranslatedAddress;
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StatusByte =
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READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus);
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if (StatusByte & 0x80) {
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HalDisplayString ("NMI: Parity Check / Parity Error\n");
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}
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if (StatusByte & 0x40) {
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HalDisplayString ("NMI: Channel Check / IOCHK\n");
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}
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//
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// This is an Isa machine, no extnded nmi information, so just do it.
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//
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KeBugCheck(NMI_HARDWARE_FAILURE);
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return(TRUE);
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}
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UCHAR
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HalpAcknowledgeEisaInterrupt(
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PVOID ServiceContext
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)
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/*++
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Routine Description:
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Acknowledge the EISA interrupt from the programmable interrupt controller.
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Return the vector number of the highest priority pending interrupt.
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Arguments:
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ServiceContext - Service context of the interrupt service supplies
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a pointer to the EISA interrupt acknowledge register.
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Return Value:
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Return the value of the highest priority pending interrupt.
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--*/
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{
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UCHAR InterruptVector;
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//
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// Read the interrupt vector from the PIC.
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//
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InterruptVector = READ_PORT_UCHAR(ServiceContext);
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return( InterruptVector );
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}
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VOID
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HalpAcknowledgeClockInterrupt(
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VOID
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)
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/*++
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Routine Description:
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Acknowledge the clock interrupt from the interval timer. The interval
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timer for EB66 comes from the Dallas real-time clock.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Acknowledge the clock interrupt by reading the control register C of
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// the Real Time Clock.
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//
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HalpReadClockRegister( RTC_CONTROL_REGISTERC );
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return;
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}
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VOID
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HalpInitializePciInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the PCI device interrupt mask.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Initialize the shadow copies of the interrupt masks to enable only
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// the SIO interrupt.
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//
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IntMask0 = (UCHAR)SIO_INTERRUPT_MASK;
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IntMask1 = 0;
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IntMask2 = 0;
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//
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// Write the masks.
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//
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WRITE_PORT_UCHAR(INTERRUPT_MASK0_QVA, ~IntMask0);
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WRITE_PORT_UCHAR(INTERRUPT_MASK1_QVA, ~IntMask1);
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if (INTERRUPT_MASK2_QVA != NULL) {
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WRITE_PORT_UCHAR(INTERRUPT_MASK2_QVA, ~IntMask2);
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}
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}
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