427 lines
10 KiB
C
427 lines
10 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1994 FirePower Systems, Inc.
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Module Name:
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pxaipsup.h
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Abstract:
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The module defines the structures, and defines for the
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AIP (Intel 82091AA) Advanced Integrated Peripheral chip.
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Author:
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Revision History:
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--*/
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fp82091.h $
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* $Revision: 1.5 $
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* $Date: 1996/05/14 02:32:08 $
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* $Locker: $
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*/
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// AIP configuration registers
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//
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// Index register select
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//
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#define AIPID 0x00 // Product Identification
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#define AIPREV 0x01 // Revision Identification
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#define AIPCFG1 0x02 // AIP Configuration 1
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#define AIPCFG2 0x03 // AIP Configuration 2
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#define FCFG1 0x10 // FDC Configuration
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#define FCFG2 0x11 // FDC Power Management and
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/* Status */
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#define PCFG1 0x20 // Parallel Port Configuration
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#define PCFG2 0x21 // Parallel Port Power Management
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/* and Status */
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#define SACFG1 0x30 // Serial Port A Configuration
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#define SACFG2 0x31 // Serail Port A Power Management
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/* and Status */
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#define SBCFG1 0x40 // Serial Port B Configuration
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#define SBCFG2 0x41 // Serial Port B Power Management
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/* and Status */
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#define IDECFG 0x50 // IDE Configuration
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/*+++
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AIPID: RO
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7-0 Product Identification Number
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AIPREV: RO
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7-4 Step Number
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3-0 Dash Number
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AIPCFG1: R/W
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7 Not Used
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6 Supply Voltage (RO)
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0: 5.0V
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1: 3.3V
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4-5 Configuration Mode Select (R/W)
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0x00 Software Motherboard
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0x01 Software Add-in
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0x10 Extended Hardware
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0x11 Basic Hardware
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3 Configuration Address Select (RO)
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0: Secondary Address
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1: Primary Address
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2-1 Reserved
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0 Clock Off (R/W)
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0: AIP powered on
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1: AIP powered off
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AIPCFG2: R/W
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7 IRQ7 Mode Select (R/W)
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0: Active High
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1: Active Low
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6 IRQ6 Mode Select (R/W)
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0: Active High
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1: Active Low
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5 IRQ5 Mode Select (R/W)
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0: Active High
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1: Active Low
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4 IRQ4 Mode Select (R/W)
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0: Active High
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1: Active Low
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3 IRQ3 Mode Select (R/W)
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0: Active High
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1: Active Low
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2-0 Reserved
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FCFG1: R/W
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7 Floppy Disk Drive Quantity (R/W)
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0: Two
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1: Four
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6-2 Reserved
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1 FDC Address Select (R/W)
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0: Primary (3F0-3F7)
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1: Secondary (370-377)
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0 FDC Enable (R/W)
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0: Disable
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1: Enable
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FCFG2: R/W
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7-4 Reserved
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3 FDC Auto Powerdown Enable (R/W)
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0: Disable
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1: Enable, 0: Disable
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2 FDC Reset (R/W)
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0: No FDC Module Reset
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1: Reset FDC Module, 0: No FDC Module Reset
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1 FDC Idle Status (RO)
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0: Active
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1: Idle, 0: Active
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0 FDC Direct Powerdown Control (R/W)
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0: Not in Direct Powerdown
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1: Powerdown, 0: Not in Direct Powerdown
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PCFG1: R/W
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7 PP FIFO Threshold Select (R/W)
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0: 8 (forward and reverse)
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1: 1 (forward), 15(reverse)
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6-5 PP Hardware Mode Select (R/W)
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00: ISA-Compatible (read), ISA-Compatible (write)
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01: PS/2-Compatible (read), PS/2-Compatible (write)
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10: EPP (read) , EPP (write)
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11: ECP (read), Reserved (do not write)
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4 Reserved
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3 PP Interrupt Select (R/W)
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0: IRQ5
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1: IRQ7
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2-1 PP Address Select (R/W)
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00: 378-37F
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01: 278-27F
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10: 3BC-3BE
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11: Reserved
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0 PP Enable (R/W)
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0: Disable
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1: Enable
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PCFG2: R/W
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7-6 Reserved
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5 PP FIFO Error Status (RO)
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0: No Underrun or Overrun
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1: Underrun or Overrun
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4 Reserved
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3 PP Auto Powerdown Enable (R/W)
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0: Disable
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1: Enable
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2 PP Reset (R/W)
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0: Inactive
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1: Active
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1 PP Idle Status (RO)
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0: Avtive
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1: Idle
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0 PP Port Direct Powerdown (R/W)
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0: Disabled
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1: Enabled
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SACFG1: R/W
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7 MIDI Clock Enable for Serial Port A (R/W)
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0: 1.8642 MHz Clock
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1: 2MHz Clock
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6-5 Reserved
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4 Serial Port A IRQ Select (R/W)
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0: IRQ3
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1: IRQ4
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3-1 Serial Port A Address Select (R/W)
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000: 3F8-3FF
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001: 2F8-2FF
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010: 220-227
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011: 228-22F
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100: 238-23F
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101: 2E8-2EF
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110: 338-33F
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111: 3E8-3EF
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0 Serial Port A Enable (R/W)
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0: Disable
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1: Enable
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SACFG2: R/W
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0: to Disable
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1: to Enable
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-------------------------------------------------------------
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7-5 Reserved
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4 Serial Port A Test Mode (R/W)
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3 Serial Port A Auto Powerdown Enable (R/W)
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2 Serial Port A Reset (R/W)
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1 Serial Port A Idle Status (RO)
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0 Serial Port A Direct Powerdown Control (R/W)
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SBCFG1: R/W
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-------------------------------------------------------------
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7 MIDI Clock Enable for Serial Port B (R/W)
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0: 1.8642 MHz Clock
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1: 2MHz Clock
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6-5 Reserved
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4 Serial Port B IRQ Select (R/W)
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0: IRQ3
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1: IRQ4
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3-1 Serial Port B Address Select (R/W)
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000: 3F8-3FF
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001: 2F8-2FF
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010: 220-227
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011: 228-22F
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100: 238-23F
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101: 2E8-2EF
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110: 338-33F
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111: 3E8-3EF
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0 Serial Port B Enable (R/W)
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0: Disable
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1: Enable
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SBCFG2: R/W
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-------------------------------------------------------------
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7-5 Reserved
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4 Serial Port B Test Mode (R/W)
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0: Disable
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1: Enable
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3 Serial Port B Auto Powerdown Enable (R/W)
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0: Disable
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1: Enable
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2 Serial Port B Reset (R/W)
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0: Reset Inactive
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1: Reset Active
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1 Serial Port B Idle Status (RO)
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0: Active
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1: Idle
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0 Serial Port B Direct Powerdown Control (R/W)
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0: Disable
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1: Enable
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IDECFG: R/W
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7-3 Reserved
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2 IDE Dual Interface Select (R/W)
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1: Primary and Secondary Address Selected
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0: Dual Interface Disabled
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1 IDE Address Select (R/W)
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0: Primary (1F0-1F7,3F6,3F7)
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1: Secondary (170-17F,376,377)
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0 IDE Interface Enable (R/W)
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0: Disable
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1: Enable, 0: Disable
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---*/
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//
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// Data register values
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//
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//
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// AIPCFG1
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//
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#define CLOCK_POWERED_ON 0x00
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#define CLOCK_POWERED_OFF 0x01
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#define PRIMARY_ADDRESS_CONFIG 0x00
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#define SECONDARY_ADDRESS_CONFIG 0x08
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#define SOFTWARE_MOTHERBOARD 0x00
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#define SOFTWARE_ADDIN 0x10
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#define EXTENDED_HARDWARE 0x20
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#define BASIC_HARDWARE 0x30
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#define SUPPLY_VOLTAGE_33V 0x40
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//
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// AIPCFG2
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//
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#define IRQ3_ACTIVE_LOW 0x08
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#define IRQ3_ACTIVE_HIGH 0x00
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#define IRQ4_ACTIVE_LOW 0x10
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#define IRQ4_ACTIVE_HIGH 0x00
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#define IRQ5_ACTIVE_LOW 0x20
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#define IRQ5_ACTIVE_HIGH 0x00
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#define IRQ6_ACTIVE_LOW 0x40
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#define IRQ6_ACTIVE_HIGH 0x00
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#define IRQ7_ACTIVE_LOW 0x80
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#define IRQ7_ACTIVE_HIGH 0x00
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#define AIPCFG2_MASK 0xF8
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//
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// FCFG1
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//
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#define FDC_ENABLE 0x01
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#define PRIMARY_FDC_ADDRESS 0x00
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#define SECONDARY_FDC_ADDRESS 0x02
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#define TWO_DISK_DRIVES 0x00
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#define FOUR_DISK_DRIVES 0x80
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#define FCFG1_MASK 0x83
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//
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// FCFG2
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//
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#define FDC_DIRECT_POWERDOWN 0x01
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#define FDC_IDLE 0x02 /* read-only */
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#define RESET_FDC_MODULE 0x04
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#define FDC_AUTO_POWERDOWN_ENABLE 0x08
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#define FCFG2_MASK 0x0F
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//
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// PCFG1
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//
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#define PP_ENABLE 0x01
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#define PP_ADDRESS_SELECT_0 0x00 /* 378-37F */
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#define PP_ADDRESS_SELECT_1 0x02 /* 278-27F */
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#define PP_ADDRESS_SELECT_2 0x04 /* 3BC-3BE */
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#define PP_IRQ7 0x08
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#define PP_IRQ5 0x00
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#define PP_HWMODE_ISA_COMPAT 0x00
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#define PP_HWMODE_PS2_COMPAT 0x20
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#define PP_HWMODE_EPP 0x40
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#define PP_HWMODE_ECP 0x60 /* read-only */
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#define PP_FIFO_THRSEL_1 0x80
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#define PP_FIFO_THRSEL_8 0x00
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#define PCFG1_MASK 0xEF
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//
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// PCFG2
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//
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#define PP_DIRECT_POWERDOWN 0x01
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#define PP_IDLE 0x02 /* read-only */
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#define PP_RESET 0x04
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#define PP_AUTO_POWERDOWN_ENABLE 0x08
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#define PP_FIFO_UNDERRUN_OR_OVERRUN 0x20
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#define PCFG2_MASK 0x2F
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//
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// SACFG1
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//
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#define PORTA_ENABLE 0x01
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#define PORTA_ADDRESS_SELECT_0 0x00 /* 3F8-3FF */
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#define PORTA_ADDRESS_SELECT_1 0x02 /* 2F8-2FF */
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#define PORTA_ADDRESS_SELECT_2 0x04 /* 220-227 */
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#define PORTA_ADDRESS_SELECT_3 0x06 /* 228-22F */
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#define PORTA_ADDRESS_SELECT_4 0x08 /* 238-23F */
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#define PORTA_ADDRESS_SELECT_5 0x0A /* 2E8-2EF */
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#define PORTA_ADDRESS_SELECT_6 0x0C /* 338-33F */
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#define PORTA_ADDRESS_SELECT_7 0x0D /* 3E8-3EF */
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#define PORTA_IRQ4 0x10
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#define PORTA_IRQ3 0x00
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#define PORTA_MIDI_CLOCK_2000KHZ 0x80
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#define PORTA_MIDI_CLOCK_1846KHZ 0x00
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#define SACFG1_MASK 0x9F
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//
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// SACFG2
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//
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#define PORTA_DIRECT_POWERDOWN 0x01
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#define PORTA_IDLE 0x02 /* read-only */
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#define PORTA_RESET 0x04
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#define PORTA_AUTO_POWERDOWN_ENABLE 0x08
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#define PORTA_TEST_MODE_ENABLE 0x10
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#define SACFG2_MASK 0x1F
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//
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// SBCFG1
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//
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#define PORTB_ENABLE 0x01
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#define PORTB_ADDRESS_SELECT_0 0x00 /* 3F8-3FF */
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#define PORTB_ADDRESS_SELECT_1 0x02 /* 2F8-2FF */
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#define PORTB_ADDRESS_SELECT_2 0x04 /* 220-227 */
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#define PORTB_ADDRESS_SELECT_3 0x06 /* 228-22F */
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#define PORTB_ADDRESS_SELECT_4 0x08 /* 238-23F */
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#define PORTB_ADDRESS_SELECT_5 0x0A /* 2E8-2EF */
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#define PORTB_ADDRESS_SELECT_6 0x0C /* 338-33F */
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#define PORTB_ADDRESS_SELECT_7 0x0D /* 3E8-3EF */
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#define PORTB_IRQ4 0x10
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#define PORTB_IRQ3 0x00
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#define PORTB_MIDI_CLOCK_2000KHZ 0x80
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#define PORTB_MIDI_CLOCK_1846KHZ 0x00
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#define SBCFG1_MASK 0x9F
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//
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// SBCFG2
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//
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#define PORTB_DIRECT_POWERDOWN 0x01
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#define PORTB_IDLE 0x02 /* read-only */
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#define PORTB_RESET 0x04
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#define PORTB_AUTO_POWERDOWN_ENABLE 0x08
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#define PORTB_TEST_MODE_ENABLE 0x10
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#define SBCFG2_MASK 0x1F
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//
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// IDECFG
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//
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#define IDE_INTERFACE_ENABLE 0x01
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#define PRIMARY_IDE_ADDRESS 0x00
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#define SECONDARY_IDE_ADDRESS 0x02
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#define IDE_DUAL_INTERFACE 0x04
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#define IDECFG_MASK 0x07
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typedef struct _INTEL_AIP_CONTROL {
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UCHAR Reserved1[0x22];
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UCHAR AIPConfigIndexRegister; // Offset 0x22
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UCHAR AIPConfigTargetRegister; // Offset 0x23
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// UCHAR Reserved1[0x26E];
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// UCHAR AIPConfigIndexRegister; // Offset 0x26E
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// UCHAR AIPConfigTargetRegister; // Offset 0x26F
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} INTEL_AIP_CONTROL, *PINTEL_AIP_CONTROL;
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